Conversion VHDL to VERILOG microprocessor?

[ozkan]

hi...
i'm trying to convert a simple microprocessor code which is writen in
VHDL to the VERILOG!
i convert the sequncer part of the code i couldn't simulate it
correctly? i added the both vhdl code and verilog code of the
sequencer...
if anyone see any mistake... please help me??it's so urgent!!

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sequencer_vhdl is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
z_flag : in STD_LOGIC;
op : in opcode;
ACC_bus : out STD_LOGIC;
load_ACC : out STD_LOGIC;
PC_bus : out STD_LOGIC;
load_PC : out STD_LOGIC;
load_IR : out STD_LOGIC;
load_MAR : out STD_LOGIC;
MDR_bus : out STD_LOGIC;
load_MDR : out STD_LOGIC;
ALU_ACC : out STD_LOGIC;
ALU_add : out STD_LOGIC;
ALU_sub : out STD_LOGIC;
INC_PC : out STD_LOGIC;
Addr_bus : out STD_LOGIC;
CS : out STD_LOGIC;
R_NW : out STD_LOGIC);
end sequencer_vhdl;

architecture rtl of sequencer_vhdl is
type state is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10);
signal present_state, next_state : state;

begin
seq : process (clock, reset) is
begin
if reset = '1' then
present_state <= s0;
elsif rising_edge(clock) then
present_state <= next_state;
endif;
end process seq;
com : process (present_state, op, z_flag) is
begin
--reset all the control signals to default
ACC_bus <= '0';
load_ACC <= '0';
PC_bus <= '0';
load_PC <= '0';
load_IR <= '0';
load_MAR <= '0';
MDR_bus <= '0';
load_MDR <= '0';
ALU_ACC <= '0';
ALU_add <= '0';
ALU_sub <= '0';
INC_PC <= '0';
Adrr_bus <= '0';
CS <= '0';
R_NW <= '0';

case present_state is
when s0 =>
PC_bus <= '1';
load_MAR <= '1';
INC_PC <= '1';
load_PC <= '1';
next_state <= S1;
when s1 =>
CS <= '1';
R_NW <= '1';
next_state <= S2;
when s2 =>
MDR_bus <= '1';
load_IR <= '1';
next_state <= S3;

when s3 =>
Adrr_bus <= '1';
load_MAR <= '1';
if op = store then
next_state <= S4;
else
next_state <= S6;
end if;

when s4 =>
ACC_bus <= '1';
load_MDR <= '1';
next_state <= S5;

when s5 =>
CS <= '1';
next_state <= S0;

when s6 =>
CS <= '1';
R_NW <= '1';
if op = load then
next_state <= S7;
elsif op = bne then
if z_flag = '0' then
next_state <= S9;
else
next_state <= S10;
end if;
else
next_state <= S8;
end if;

when s7 =>
MDR_bus <= '1';
load_ACC <= '1';
next_state <= S0;

when s8 =>
MDR_bus <= '1';
ALU_ACC <= '1';
load_ACC <= '1';
next_state <= S0;
if op = add then
ALU_add <= '1';
elsif op = sub then
ALU_sub <= '1';
end if;

when s9 =>
MDR_bus <= '1';
load_PC <= '1';
next_state <= S0;

when s10 =>
next_state <= S0;

end case;
end process com;
end architecture rtl;


VERILOG CODE:

module sequencer_1(ACC_bus, load_ACC, PC_bus, load_PC, load_IR,
load_MAR, MDR_bus, load_MDR, ALU_ACC, ALU_sub, INC_PC, Adrr_bus, CS,
R_NW, clock, reset, z_flag, op, ALU_add);
output ACC_bus;
output load_ACC;
output PC_bus;
output load_PC;
output load_IR;
output load_MAR;
output MDR_bus;
output load_MDR;
output ALU_ACC;
output ALU_sub;
output INC_PC;
output Adrr_bus;
output CS;
output R_NW;
input clock;
input reset;
input z_flag;
input op;
output ALU_add;

reg[3:0] present_state,next_state;
parameter[3:0] S0=4'B0000, S1=4'B0001, S2=4'B0010,
S3=4'B0011, S4=4'B0100, S5=4'B0101,
S6=4'B0110, S7=4'B0111, S8=4'B1000,
S9=4'B1001, S10=4'B1010;

always @(posedge clock or posedge reset)

if (reset)
present_state <= S0;

else if(clock)
present_state <= next_state;

always @(present_state or op or z_flag)

begin
ACC_bus <= 1'b0;
load_ACC <= 1'b0;
PC_bus <= 1'b0;
load_PC <= 1'b0;
load_IR <= 1'b0;
load_MAR <= 1'b0;
MDR_bus <= 1'b0;
load_MDR <= 1'b0;
ALU_ACC <= 1'b0;
ALU_sub <= 1'b0;
INC_PC <= 1'b0;
Adrr_bus <= 1'b0;
CS <= 1'b0;
R_NW <= 1'b0;
ALU_add <= 1'b0;

case (present_state)
S0: begin
PC_bus <= 1'b1;
load_MAR <= 1'b1;
INC_PC <= 1'b1;
load_PC <= 1'b1;
next_state <= S1;
end
S1: begin
CS <= 1'b1;
R_NW <= 1'b1;
next_state <= S2;
end
S2: begin
MDR_bus <= 1'b1;
load_IR <= 1'b1;
next_state <= S3;
end
S3: begin
Adrr_bus <= 1'b1;
load_MAR <= 1'b1;
if(op == store)
next_state <= S4;
else
next_state <= S6;
end
S4: begin
ACC_bus <= 1'b1;
load_MDR <= 1'b1;
next_state <= S5;
end
S5: begin
CS <= 1'b1;
next_state <= S0;
end
S6: begin
CS <= 1'b1;
R_NW <= 1'b1;
if(op == load)
next_state <= S7;
else if(op == bne)
begin
if(z_flag)
next_state <= S9;
else
next_state <= S10;
end
else
next_state <= S8;
end
S7: begin
MDR_bus <= 1'b1;
load_ACC <= 1'b1;
next_state <= S0;
end
S8: begin
MDR_bus <= 1'b1;
ALU_ACC <= 1'b1;
load_ACC <= 1'b1;
next_state <= S0;
if (op == add)
ALU_add <= 1'b1;
else if (op == sub)
ALU_sub <= 1'b1;
end
S9: begin
MDR_bus <= 1'b1;
load_PC <= 1'b1;
next_state <= S0;
end
S10: next_state <= S0;

endcase;

end


endmodule
......................................................................
i'm think the problem on the opcode part?? so the cpu_defns is in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.all;

package cpu_defs is


type opcode is (load, store, add, sub, bne);

-- Declare constants

constant word_w : NATURAL := 8;
constant op_w : NATURAL := 3;
constant rfill : std_logic_vector(op_w - 1 downto 0)
:= (others => '0');
-- Declare functions and procedure

function slv2op (slv : in std_logic_vector) return opcode;

function op2slv (op : in opcode) return std_logic_vector;

end cpu_defs;


package body cpu_defs is

type optable is array (opcode)
of std_logic_vector(op_w - 1 downto 0);

constant trans_table : optable
:= ("000", "001", "010", "011", "100");
function op2slv (op : in opcode) return std_logic_vector is

begin

return transtable(op);
end function op2slv;


-- Example 2
function slv2op (slv : in std_logic_vector) return opcode is

variable transop : opcode;
begin
for i in opcode loop
if (slv = trans_table(i)) then
transop := i;
end if;
end loop;

return transop;

end function slv2op;

end package body cpu_defs;
-------------------------------------------------------------------------------------

 

[PeteS]

Mike Treseler wrote:

ozkan wrote:

i'm trying to convert a simple microprocessor code which is writen in
VHDL to the VERILOG!

1. Correct the syntax errors,
missing signal declarations,
and missing package use clause
in the vhdl version.

2. Simulate the vhdl version
to make sure it is worthy
of any further effort.

-- Mike Treseler

Having performed the excellent suggestions Mike makes, if it is then
worth further effort, figure out the various functions implemented in
VHDL and then implement them in Verilog.

It really isn't hard if it's cleanly written in the first place. I'm
doing this right now with the Cool Runner II + SPI flash app note to
configure a Spartan 3. Fortunately, the code and description is *very*
clearly done, so it's not a particularly hard project.

Cheers

PeteS

 

[Mark McDougall]

Mike Treseler wrote:

2. Simulate the vhdl version
to make sure it is worthy
of any further effort.

It's probably worth at least 10% of the final mark, so probably *is*
worth it... ?!?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Mike Treseler]

ozkan wrote:

i'm trying to convert a simple microprocessor code which is writen in
VHDL to the VERILOG!

1. Correct the syntax errors,
missing signal declarations,
and missing package use clause
in the vhdl version.

2. Simulate the vhdl version
to make sure it is worthy
of any further effort.

-- Mike Treseler