Conversion from Real to Std_logic??

[kwaj]

Is there a command to do this?

- Kwaj

--
- Kwaj
http://alpha400.ee.unsw.edu.au/~p3015094

 

[Srinivasan Venkataramanan]

Hi Kwaj,
Few years back I wrote a package to do this, in-line with
$realtobits and $bitstoreal of Verilog. Unfortunately, I don't have them any
more. There is a (beta ??) FPHDL package, see
http://www.eda.org/fphdl/hm/0011.html

HTH,
Srinivasan
--
Srinivasan Venkataramanan
Senior Verification Engineer, Intel Bangalore, India
Co-Author of: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition,
2004 isbn 0-9705394-6-0, Ben Cohen, Srinivasan & Ajeetha

http://www.noveldv.com
I don't speak for Intel

"kwaj" <k.otengNOSPAM@student.unsw.edu.auNOSPAM> wrote in message
news:c0928s$ot9$1@tomahawk.unsw.edu.au...

Is there a command to do this?

- Kwaj

--
- Kwaj
http://alpha400.ee.unsw.edu.au/~p3015094