Convergence Problem

[Debjit]

Hi All,

I am facing a typical problem of convergence. My aim is to find out
the verification speedup for the Large AMS circuits by using
behavioral models. To write the behavioral models , I have used
Verilog-A code. I am using cadence spectreVerilog. But to my utter
disappointment I found that the Convergence is the main culprit for
the simulation speedup. Can any one suggest how to get rid of this
problem? Is it advisable to choose some integration method in the
Cadence ADE window like euler or trapezoidal or anything else?

Please suggest as soon as possible.

Thanking you,

Yours sincerely,
Debjit
======================
Debjit Pal
MS Student and Research Consultant
Department of Computer Science and Engineering
IIT Kharagpur

 

[Riad KACED]

Hi Debjit,

You ar a new user of Cadence as far as i remember. Besides I recall
having helped you with some issue running AMS Designer. Why are you
going back to that old spectreVerilog then ?
Anyway, convergence problems are not easy to debug, but if you open
the Spectre doc, you will find a whole section talking of how to solve
convergence problems. Besides, I have seen across my humble experience
that some convergence problems are related to design, floating inputs
is one common thing I have seen.
If you really want to get rid of your convergence problems, then you
could consider real-value modeling with wreals in Verilog-AMS. wreal
real is all managed by the digital solver that does not know any
convergence problems. I think it is because the fact digital solvers
are event driven, not 100% sure it is the main reason though. Andrew
may comment this I suppose.

BTW, when you hit convergence problems, the log usually gives some
clues, have you considered those ?

Cheers,
Riad.

 

[Debjit]

On Oct 16, 2:08 am, Riad KACED <riad.ka...@gmail.com> wrote:

Hi Debjit,

You ar a new user of Cadence as far as i remember. Besides I recall
having helped you with some issue running AMS Designer. Why are you
going back to that old spectreVerilog then ?
Anyway, convergence problems are not easy to debug, but if you open
the Spectre doc, you will find a whole section talking of how to solve
convergence problems. Besides, I have seen across my humble experience
that some convergence problems are related to design, floating inputs
is one common thing I have seen.
If you really want to get rid of your convergence problems, then you
could consider real-value modeling with wreals in Verilog-AMS. wreal
real is all managed by the digital solver that does not know any
convergence problems. I think it is because the fact digital solvers
are event driven, not 100% sure it is the main reason though. Andrew
may comment this I suppose.

BTW, when you hit convergence problems, the log usually gives some
clues, have you considered those ?

Cheers,
Riad.

Hi Riad,
I am working in spectre for quite a long time. But really I am a new
bee for the spectreVerilog. I am working in a project in my University
i.e. IIT Kharagpur which is funded by NSUK. The only mean we have to
simulate their IP is spectreVerilog as they are not willing to switch
to AMS right now, though for my personal work I prefer AMS. I have
considered the log and got rid from the Convergence Issues upto a
certain extent. I will consider the wreal as you suggested shortly, as
you suggested and will post my experience and problems, if any.

Thanks for your help.

Cheers!!!!
Debjit.