Convergence Problem??

R

Ramana Tadepalli

Guest
Hi,
I run into the following error when running a transient simulation for a
simple comparator set for a pipelined ADC. This error occurs only on a
process corner simulation.
---------------------
Warning from spectre at time = 762.048 ns during transient analysis `tran'.
Convergence difficulties resulted in error requirements being
unsatisfied.
---------------------------
Could anyone please indicate a solution, since the simulation (3us) starts
stepping at 'as' intervals.
Also what is the implication of this problem in terms of the results
(partial) that the analog artist generates.
-Ramana
 
Ramana,

This could be due to a number of things, but often it is caused by discontinuous
device models, exacerbated by insufficient capacitance in those models (which
might smooth out the discontinuities).

Watch out for excessive component values (particularly capacitors and
inductors).

Also, you might want to try the cmin option to the tran analysis - for example,
use cmin=0.1f (say) to add a 0.1 fempto farad capacitor to all nodes. This
can help to damp any poorly controlled nodes.

I'd recommend reading Ken Kundert's book "A Designer's Guide to SPICE and
SPECTRE" (see http://www.designers-guide.com ) - it has good information
on solving convergence (DC and transient) problems.

Regards,

Andrew.

On Mon, 15 Sep 2003 02:24:38 -0700, "Ramana Tadepalli"
<rtadepalli@asu.noreply.edu> wrote:

Hi,
I run into the following error when running a transient simulation for a
simple comparator set for a pipelined ADC. This error occurs only on a
process corner simulation.
---------------------
Warning from spectre at time = 762.048 ns during transient analysis `tran'.
Convergence difficulties resulted in error requirements being
unsatisfied.
---------------------------
Could anyone please indicate a solution, since the simulation (3us) starts
stepping at 'as' intervals.
Also what is the implication of this problem in terms of the results
(partial) that the analog artist generates.
-Ramana
Click to expand...
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
 
Thanks Andrew.
I will try the solution you mentioned and will go though the book.
What is the implication of the warning in terms of the results. I am
looking specifically for switching delays. Are those affected?
-Ramana

"Andrew Beckett" <andrewb@DELETETHISBITcadence.com> wrote in message
news:q65dmvca0kja0j98hpon9imuhokojpta9u@4ax.com...
Ramana,

This could be due to a number of things, but often it is caused by
discontinuous
device models, exacerbated by insufficient capacitance in those models
(which
might smooth out the discontinuities).

Watch out for excessive component values (particularly capacitors and
inductors).

Also, you might want to try the cmin option to the tran analysis - for
example,
use cmin=0.1f (say) to add a 0.1 fempto farad capacitor to all nodes. This
can help to damp any poorly controlled nodes.

I'd recommend reading Ken Kundert's book "A Designer's Guide to SPICE and
SPECTRE" (see http://www.designers-guide.com ) - it has good information
on solving convergence (DC and transient) problems.

Regards,

Andrew.

On Mon, 15 Sep 2003 02:24:38 -0700, "Ramana Tadepalli"
rtadepalli@asu.noreply.edu> wrote:

Hi,
I run into the following error when running a transient simulation for a
simple comparator set for a pipelined ADC. This error occurs only on a
process corner simulation.
---------------------
Warning from spectre at time = 762.048 ns during transient analysis
`tran'.
Convergence difficulties resulted in error requirements being
unsatisfied.
---------------------------
Could anyone please indicate a solution, since the simulation (3us)
starts
stepping at 'as' intervals.
Also what is the implication of this problem in terms of the results
(partial) that the analog artist generates.
-Ramana


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
Click to expand...
 
Ramana,

Exactly how the results are affected is hard to say. However, it suggests that
it has not been correctly able to follow the signals in the transient analysis -
spectre (as do other circuit simulators) try to maximize the timestep between
adjacent solutions whilst still keeping the errors within acceptable tolerances
(i.e. a tradeoff of speed versus accuracy) - sometimes this may not be possible
without some assistance from you in controlling some settings.

Hopefully reading Ken's book will make this clearer (it's not as simple
as a two line answer, unfortunately).

Regards,

Andrew.

On Tue, 16 Sep 2003 03:33:44 -0700, "Ramana Tadepalli"
<rtadepalli@asu.noreply.edu> wrote:

Thanks Andrew.
I will try the solution you mentioned and will go though the book.
What is the implication of the warning in terms of the results. I am
looking specifically for switching delays. Are those affected?
-Ramana

"Andrew Beckett" <andrewb@DELETETHISBITcadence.com> wrote in message
news:q65dmvca0kja0j98hpon9imuhokojpta9u@4ax.com...
Ramana,

This could be due to a number of things, but often it is caused by
discontinuous
device models, exacerbated by insufficient capacitance in those models
(which
might smooth out the discontinuities).

Watch out for excessive component values (particularly capacitors and
inductors).

Also, you might want to try the cmin option to the tran analysis - for
example,
use cmin=0.1f (say) to add a 0.1 fempto farad capacitor to all nodes. This
can help to damp any poorly controlled nodes.

I'd recommend reading Ken Kundert's book "A Designer's Guide to SPICE and
SPECTRE" (see http://www.designers-guide.com ) - it has good information
on solving convergence (DC and transient) problems.

Regards,

Andrew.

On Mon, 15 Sep 2003 02:24:38 -0700, "Ramana Tadepalli"
rtadepalli@asu.noreply.edu> wrote:

Hi,
I run into the following error when running a transient simulation for a
simple comparator set for a pipelined ADC. This error occurs only on a
process corner simulation.
---------------------
Warning from spectre at time = 762.048 ns during transient analysis
`tran'.
Convergence difficulties resulted in error requirements being
unsatisfied.
---------------------------
Could anyone please indicate a solution, since the simulation (3us)
starts
stepping at 'as' intervals.
Also what is the implication of this problem in terms of the results
(partial) that the analog artist generates.
-Ramana


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
Click to expand...
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
 
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