convergence issues in phase noise analysis for PLL using cad

[srini]

Hi,

I am working on phase noise simulations of pll blocks(transistor level)
at 2.4ghz in
tsmc18rf with spectre simulator using cadence.
For clock divider, the pss(periodic steady state) analysis does not
converge. it stops after 20 (or max period) iterations. also, jitter
and phase noise analysis for phase frequency detector also does not
converge. it takes long time to run and then finally reports
convergence problems.
i tried following the suggestions given in cadence documentation and n
the output log, but to no avail.
how to set the different parameters tolerances for
reltol,abstol,maxsteps,ltration,steadystate ratio. i tried loosening
some of them, still it did not yield results.
I tried the following settings"
for pss:
fundmental tone is 2.4ghz large signal input
beat period: 0.41666n or 0.83333n (tried both)
no. of harmonics: 20
accuracy settings: conservative, tsatb =800n
i have not highlighed oscillator as this is a driven circuit.
in options, maxstep is 10ps. steadyratio=1, integration method: method
is gear2only and tsabmethod =gear2only, highorder=yes,
psratio=1,maxorder=12.
for pnoise analysis,
sweep type=relative, relative harmonic=1 or 100k,
freq range = 1k to 100M
sweep type = logarithmic, points per decade =5
max. sidebands = 10 or 20(tried both)
output = voltage
input = none,
options: gear_order=3
am i making any mistake in the above settings/analysis? is there any
other way to go about this?

is there any documentation or info on this....any suggestions are
highly welcome.

thanks
srini

 

[Andrew Beckett]

On 3 Jan 2006 15:21:38 -0800, "srini" <sgsj2004@gmail.com> wrote:

Hi,

I am working on phase noise simulations of pll blocks(transistor level)
at 2.4ghz in
tsmc18rf with spectre simulator using cadence.
For clock divider, the pss(periodic steady state) analysis does not
converge. it stops after 20 (or max period) iterations. also, jitter
and phase noise analysis for phase frequency detector also does not
converge. it takes long time to run and then finally reports
convergence problems.
i tried following the suggestions given in cadence documentation and n
the output log, but to no avail.
how to set the different parameters tolerances for
reltol,abstol,maxsteps,ltration,steadystate ratio. i tried loosening
some of them, still it did not yield results.
I tried the following settings"
for pss:
fundmental tone is 2.4ghz large signal input
beat period: 0.41666n or 0.83333n (tried both)
no. of harmonics: 20
accuracy settings: conservative, tsatb =800n
i have not highlighed oscillator as this is a driven circuit.
in options, maxstep is 10ps. steadyratio=1, integration method: method
is gear2only and tsabmethod =gear2only, highorder=yes,
psratio=1,maxorder=12.
for pnoise analysis,
sweep type=relative, relative harmonic=1 or 100k,
freq range = 1k to 100M
sweep type = logarithmic, points per decade =5
max. sidebands = 10 or 20(tried both)
output = voltage
input = none,
options: gear_order=3
am i making any mistake in the above settings/analysis? is there any
other way to go about this?

is there any documentation or info on this....any suggestions are
highly welcome.

thanks
srini

First and foremost, the PSS fundamental frequency must be the frequency of the
output of your divider - it doesn't look as if you've done that (well, you
specified the beat period of half the period). You should specify it as a either
a frequency or a period, depending on which ends up being a reasonably round
number (i.e. not lots of recurring digits).

Start with errpreset=moderate. Quite likely you don't need to have 800ns tstab,
so I'd leave that blank to start off with. Similarly, you can leave maxstep
alone. Do not set steadyratio to 1. Turn off highorder - this is really only
appropriate with linear/weakly non-linear circuits.

Don't set gear_order to 3 in the pnoise - leave it alone.

The most likely explanation was getting the PSS fundamental wrong, so I'd set
everything back to defaults, correct the PSS fundamental, and start from there.
The PSS fundamental needs to contain an integer number of cycles of every signal
in the circuit - not just the input frequencies, but any subharmonics elsewhere
in the circuit.

Regards,

Andrew.