conv_std_logic vector

[foaud167]

hi
the following line of code is giving me an error and i can't understand
why.
The line in question is
outp <= conv_std_logic_vector((conv_signed(inp) sll 1), 8);

and the error is
IN mode Formal SIZE of conv_std_logic_vector with no default value must
be associated with an actual value.

thanx


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shifter is
generic (n: integer := 4);
port (inp: in std_logic_vector(2*n-1 downto 0);
outp: out std_logic_vector(2*n-1 downto 0));
end shifter;

architecture Behavioral of shifter is

begin

outp <= conv_std_logic_vector((conv_signed(inp) sll 1), 8); --ERROR

end Behavioral;

 

[Mike Treseler]

foaud167 wrote:

the following line of code is giving me an error and i can't understand

I can't understand a shift register without a clock.
Maybe this is what you had in mind.

-- Mike Treseler
____________________
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shifter is
generic (n : integer := 4);
port (inp : in std_ulogic;
clk : in std_ulogic;
outp : out std_logic_vector(2*n-1 downto 0));
end shifter; -- Sat Dec 3 14:35:30 2005 Mike Treseler
architecture Behavioral of shifter is
begin
process (clk) is
subtype my_signed_t is signed(outp'range);
variable sh_v : my_signed_t;
begin
if rising_edge(clk) then
sh_v := sh_v sll 1; -- shift left
sh_v(0) := inp; -- input bit
end if;
outp <= std_logic_vector(sh_v); -- transfer value
end process;
end Behavioral;

 

[Jim Lewis]

In this case use type conversions of the form:
outp <= std_logic_vector(signed(inp) sll 1);

These type conversions are what other languages call
type casting and are built into VHDL (although VHDL calls
them type conversions). Basically you can do this for
array types that have base values based on the same
type (std_logic) and indicies based on type (natural/integer).

For shifting, you also might want to consider using "&"

Cheers,
Jim

BTW, I also recommend that instead of:
use IEEE.STD_LOGIC_ARITH.ALL; -- a vendor package with issues

that you use:
use ieee.numeric_std.all; -- actual ieee standard
-- addresses issues in std_logic_arith

The main big difference between the two is that for conversions
between integer types and signed/unsigned types use
to_integer, to_signed, to_signed rather than the corresponding
conv_ form.

hi
the following line of code is giving me an error and i can't understand
why.
The line in question is
outp <= conv_std_logic_vector((conv_signed(inp) sll 1), 8);

and the error is
IN mode Formal SIZE of conv_std_logic_vector with no default value must
be associated with an actual value.

thanx


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shifter is
generic (n: integer := 4);
port (inp: in std_logic_vector(2*n-1 downto 0);
outp: out std_logic_vector(2*n-1 downto 0));
end shifter;

architecture Behavioral of shifter is

begin

outp <= conv_std_logic_vector((conv_signed(inp) sll 1), 8); --ERROR

end Behavioral;

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~