CONV_INTEGER ERROR

[ted.franklin3@gmail.com]

I am trying to get the simulation running for a design I inherited and
I keep getting the following compilation errors in Model Sim...

** Error: Top/Test/Models/Emb_aes.vhd(106): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(108): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(110): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(112): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(114): No feasible entries for
subprogram "conv_integer".

The lines containing the errors are shown below where the signal
"frame" is of type std_logic_vector(64 downto 0).

write(write_line, conv_integer(frame(29)));
write(write_line, conv_integer(frame(30)));
write(write_line, conv_integer(frame(31)));
write(write_line, conv_integer(frame(32)));
write(write_line, conv_integer(frame(33)));

I noticed other lines in the same process don't generate errors. Some
of those lines are shown below where CH0 and DA0 are std_logic_vector(1
downto 0) and (19 downto 0), respectively.

write(write_line, conv_integer(CH0));
write(write_line, conv_integer(DA0));

Is there an issue with using the conv_integer function with the value
being a single bit slice (a 1 or a 0) of a std_logic_vector??

 

[Paul Uiterlinden]

ted.franklin3@gmail.com wrote:

Is there an issue with using the conv_integer function with the
value being a single bit slice (a 1 or a 0) of a std_logic_vector??

Yes, conv_integer is only defined for std_logic_vector, not for
std_logic. What you can do is make a std_logic_vector with only one
element:

write(write_line, conv_integer(std_logic_vector'(0 => frame(29))));

(Assuming that frame is an array of std_logic_vector)

--
Paul.
www.aimcom.nl

 

[ted.franklin3@gmail.com]

Thanks. I figured as much but didn't see that stated anywhere.

I guess you could also do...
write(write_line, conv_integer(frame(29 downto 29)));


Paul Uiterlinden wrote:

ted.franklin3@gmail.com wrote:


Is there an issue with using the conv_integer function with the
value being a single bit slice (a 1 or a 0) of a std_logic_vector??

Yes, conv_integer is only defined for std_logic_vector, not for
std_logic. What you can do is make a std_logic_vector with only one
element:

write(write_line, conv_integer(std_logic_vector'(0 => frame(29))));

(Assuming that frame is an array of std_logic_vector)

--
Paul.
www.aimcom.nl

 

[Paul Uiterlinden]

ted.franklin3@gmail.com wrote:

Thanks. I figured as much but didn't see that stated anywhere.

I guess you could also do...
write(write_line, conv_integer(frame(29 downto 29)));

Ah, yes. That's even simpler. Works if you already have a
std_logic_vector.

If you just have a single bit (std_logic), you must use the
std_logic_vector'(0 => single_bit) trick.

--
Paul.
www.aimcom.nl

 

[Jim Lewis]

Ted,
You are working too hard. If you include the package:

use ieee.std_logic_textio.all ;

then you can write std_logic directly. Of course, you
if it is other than 0 or 1 it will print differently:

write(write_line, frame(29));

Cheers,
Jim

I am trying to get the simulation running for a design I inherited and
I keep getting the following compilation errors in Model Sim...

** Error: Top/Test/Models/Emb_aes.vhd(106): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(108): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(110): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(112): No feasible entries for
subprogram "conv_integer".
** Error: Top/Test/Models/Emb_aes.vhd(114): No feasible entries for
subprogram "conv_integer".

The lines containing the errors are shown below where the signal
"frame" is of type std_logic_vector(64 downto 0).

write(write_line, conv_integer(frame(29)));
write(write_line, conv_integer(frame(30)));
write(write_line, conv_integer(frame(31)));
write(write_line, conv_integer(frame(32)));
write(write_line, conv_integer(frame(33)));

I noticed other lines in the same process don't generate errors. Some
of those lines are shown below where CH0 and DA0 are std_logic_vector(1
downto 0) and (19 downto 0), respectively.

write(write_line, conv_integer(CH0));
write(write_line, conv_integer(DA0));

Is there an issue with using the conv_integer function with the value
being a single bit slice (a 1 or a 0) of a std_logic_vector??

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~