CONV: Mealy to Moore - Serial Adder

[Ignoramus]

This serial adder was designed as a Mealy type state machine. Can anyone
help me re-design a Verilog model for this using a Moore type state
machine create a Verilog model.

-------------------------------------------------------------

module sadd (a, b, s, clock, clear);
parameter s0 = 1’b0, s1 = 1’b1;
input a, b, clock, clear;
output s;
reg s;
reg ps, ns;

always @(posedge clock or posedge clear) begin
if (clear) begin
ps = s0;
end
else begin
ps = ns;
end
end

always @(ps or a or b) begin
case (ps)
s0: begin
case ({a,b})
2’b00: begin
ns = s0;
s = 1;
end
2’b01: begin
ns = s1;
s = 0;
end
2’b10: begin
ns = s1;
s = 0;
end
2’b11: begin
ns = s1;
s = 1;
end
s = 0;
end
2’b01: begin
ns = s0;
s = 1;
end
2’b10: begin
ns = s0;
s = 1;
end
2’b11: begin
ns = s1;
s = 0;

end
default: begin
ns = s0;
s = 0;
end
endcase
end
s1: begin
case ({a,b})
2’b00: begin
ns = s0;
default: begin
ns = s0;
s = 0;
end
endcase
end
default: begin
ns = s0;
end
endcase
end

endmodule

 

[swamy_digital]

Pass the inputs a and b through flipflops and give the output of the
flops to sadd module. That will result in a Moore machine with one
cycle delay for results.


Ignoramus wrote:

This serial adder was designed as a Mealy type state machine. Can anyone
help me re-design a Verilog model for this using a Moore type state
machine create a Verilog model.

-------------------------------------------------------------

module sadd (a, b, s, clock, clear);
parameter s0 = 1'b0, s1 = 1'b1;
input a, b, clock, clear;
output s;
reg s;
reg ps, ns;

always @(posedge clock or posedge clear) begin
if (clear) begin
ps = s0;
end
else begin
ps = ns;
end
end

always @(ps or a or b) begin
case (ps)
s0: begin
case ({a,b})
2'b00: begin
ns = s0;
s = 1;
end
2'b01: begin
ns = s1;
s = 0;
end
2'b10: begin
ns = s1;
s = 0;
end
2'b11: begin
ns = s1;
s = 1;
end
s = 0;
end
2'b01: begin
ns = s0;
s = 1;
end
2'b10: begin
ns = s0;
s = 1;
end
2'b11: begin
ns = s1;
s = 0;

end
default: begin
ns = s0;
s = 0;
end
endcase
end
s1: begin
case ({a,b})
2'b00: begin
ns = s0;
default: begin
ns = s0;
s = 0;
end
endcase
end
default: begin
ns = s0;
end
endcase
end

endmodule