B
Benjamin Couillard
Guest
Hi everyone,
I'm trying to simulate my EDK design that contains a PCI-express block
connected to a PLB bus. In the PCI express block it is mentionned that
"The MPLB_Rst and SPLB_Rst must be asserted simultaneously and held
for a minimum of 300 ns". I connected the reset as suggested in the
plbv46_pcie datasheet, however myst resets only last about 85 ns. It
doesn't matter how long my reset input is since the block
"proc_sys_reset_0" seems to be edge sensitive and only triggers the
PLB_reset when my external reset goes from 0 to 1.
Is there a way to force "proc_sys_reset" to generate resets of 300 ns
or more?
Best regards
I'm trying to simulate my EDK design that contains a PCI-express block
connected to a PLB bus. In the PCI express block it is mentionned that
"The MPLB_Rst and SPLB_Rst must be asserted simultaneously and held
for a minimum of 300 ns". I connected the reset as suggested in the
plbv46_pcie datasheet, however myst resets only last about 85 ns. It
doesn't matter how long my reset input is since the block
"proc_sys_reset_0" seems to be edge sensitive and only triggers the
PLB_reset when my external reset goes from 0 to 1.
Is there a way to force "proc_sys_reset" to generate resets of 300 ns
or more?
Best regards