controlling data bus access

Hey everyone,

I've looking for some pointers on controlling data bus access in a
project of mine.

I have at least 3 modules that are connected to a 14bit data bus and
i'm just wondering what wud be a gud scheme (with low overhead) to
moderate write access to the data bus such that no data is lost.

Does anyone have any gud locations to start looking on the web maybe?

Cheers,


Rob.

 

I'm not sure about web pages describing this problem specifically. But
one thing I might try that's relatively simple is to implement some
sort of bus mastering scheme. One of these devices, probably the
highest priority one, could be a "master". The other two devices would
request access to the bus by asserting a signal. When a device is
finally granted bus access it will have one of it's lines asserted so
it knows what to do.