control circuit for a bus

[danaitsa_thebest@hotmail.]

Hello to everyone,
I have to implement a control circuit for a bus.The bus has a control
circuit that swaps the values of 4 registers(8-bit each one):R1,R2,R3
and R4.The architecture of that bus should use the tri-state device.The
control circuit should have 3 inputs w,I(0) and I(1) and do the
following:

1.When I(1)=0,I(0)=0,w=1 then it swaps the values of R1,R2 & R3
2.When I(1)=0,I(0)=1,w=1 then it swaps(from left to right) the values
of R1,R2 & R3 with the help of R4
3.When I(1)=1,I(0)=0,w=1 then it swaps(from right to left)the values of
R1,R2 & R3 with the help of R4
4.When I(1)=1,I(0)=1,w=0 then it should do nothing

What I have done so far is the following:

--A programme for each register:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;

ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Rin = '1' THEN
Q <= R ;
END IF ;
END PROCESS ;
END Behavior ;


--A programme for the tri-state device:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY trin IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
E : IN STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END trin ;

ARCHITECTURE Behavior OF trin IS
BEGIN
F <= (OTHERS => 'Z') WHEN E = '0' ELSE X ;
END Behavior ;

-- A programme for the control-circuit

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY shiftr IS
GENERIC ( K : INTEGER := 4 ) ;
PORT ( Resetn, Clock, w : IN STD_LOGIC ;
I : IN STD_LOGIC_VECTOR(0 TO 1) ;
Q : BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;
END shiftr ;

ARCHITECTURE Behavior OF shiftr IS
BEGIN
PROCESS ( Resetn, Clock , I )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
IF I(1)='0' AND I(0)='0' THEN
Genbits: FOR i IN K DOWNTO 2 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;

ELSIF I(1)='0' AND I(0)='1' THEN
Genbits1: FOR i IN K DOWNTO 2 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;

ELSIF I(1)='1' AND I(0)='0' THEN
Genbits2: FOR i IN K DOWNTO 2 LOOP
Q(i-1) <= Q(i) ;
END LOOP ;
END IF;
Q(1) <= w ;
END IF ;
END PROCESS ;
END Behavior ;

--A programme for the package:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

PACKAGE components IS

COMPONENT regn -- register
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END COMPONENT ;

COMPONENT shiftr -- shift register with async reset
GENERIC ( K : INTEGER := 4 ) ;
PORT ( Resetn, Clock, w : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;
END component ;

COMPONENT trin -- tri-state buffers
GENERIC ( N : INTEGER := 8 ) ;
PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
E : IN STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END COMPONENT ;

--A programme for the bus:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.components.all ;

ENTITY swap IS
PORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Resetn, w : IN STD_LOGIC ;
Clock, Extern : IN STD_LOGIC ;
RinExt : IN STD_LOGIC_VECTOR(1 TO 4) ;
BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END swap ;

ARCHITECTURE Behavior OF swap IS
SIGNAL Rin, Rout,Q: STD_LOGIC_VECTOR(1 TO 4) ;
SIGNAL R1, R2, R3,R4 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
BEGIN
control: shiftr GENERIC MAP ( K => 4 )
PORT MAP ( Resetn, Clock, w, Q ) ;
Rin(1) <= RinExt(1) OR Q(4) ;
Rin(2) <= RinExt(2) OR Q(3) ;
Rin(3) <= RinExt(3) OR Q(2) ;
Rin(4) <= RinExt(4) OR Q(1) ;
Rout(1) <= Q(3) ; Rout(2) <= Q(2) ; Rout(3) <= Q(1) ; Rout(4)<=Q(4);

tri_ext: trin PORT MAP ( Data, Extern, BusWires ) ;
reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;
reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;
reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;
reg4: regn PORT MAP ( BusWires, Rin(4), Clock, R4 ) ;
tri1: trin PORT MAP ( R1, Rout(1), BusWires ) ;
tri2: trin PORT MAP ( R2, Rout(2), BusWires ) ;
tri3: trin PORT MAP ( R3, Rout(3), BusWires ) ;
tri4: trin PORT MAP ( R4, Rout(4), BusWires ) ;
END Behavior ;

Everything works fine except for the control circuit where I need your
help as I am an amateur user of VHDL.

 

[danaitsa_thebest@hotmail.]

Where I need your help is the following programme:

-- A programme for the control-circuit

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY shiftr IS
GENERIC ( K : INTEGER := 4 ) ;
PORT ( Resetn, Clock, w : IN STD_LOGIC ;
I : IN STD_LOGIC_VECTOR(0 TO 1) ;
Q : BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;
END shiftr ;

ARCHITECTURE Behavior OF shiftr IS
BEGIN
PROCESS ( Resetn, Clock , I )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
IF I(1)='0' AND I(0)='0' THEN
Genbits: FOR i IN K DOWNTO 2 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;

ELSIF I(1)='0' AND I(0)='1' THEN
Genbits1: FOR i IN K DOWNTO 2 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;

ELSIF I(1)='1' AND I(0)='0' THEN
Genbits2: FOR i IN K DOWNTO 2 LOOP
Q(i-1) <= Q(i) ;
END LOOP ;
END IF;
Q(1) <= w ;
END IF ;
END PROCESS ;
END Behavior ;