Continous assign statement in clock: is it safe?

[Paul Uiterlinden]

I have a general question: is it safe to have a continuous assign
statement in a clock line, or does this introduce a race condition?

A certain simulation (which has an assignment in a clock line) passes in
ModelSim, but fails in ncsim (only when delay_mode is set to unit, as I
found out later).

Below is some code that I created to reproduce the error. Whatever I try
though, q1, q2 and q3 correctly clock in the data from before the rising
clock edge, so I'm not quite sure whether the assign im the clock is a
prolem or not.

Paul.



module assign_in_clk;
reg clk;
wire clk_1;
wire clk_2;
reg d1;
reg q1;
reg q2;
reg q3;

// Clock generator
//
initial
begin
clk = 1'b0;
repeat (10) #50 clk = !clk;
end

// Flipflops on normal clock
//
always @(posedge clk)
begin
q1 <= d1;
q3 <= q2;
end

// Flipflop on renamed clock (via assign statement)
//
always @(posedge clk_2)
begin
q2 <= q1;
end

// Data generator
//
initial
begin
d1 = 1'b0;
wait(clk == 1'b0);
repeat (5) #100 d1 = !d1;
end

// Assignments in clock
//
assign clk_2 = clk_1;
assign clk_1 = clk;
endmodule