Constants and functions question. Xilinx ISE error...

Hello, i've got a really frustrating problem.
In my package i declare these constants and functions:

function LOG2(x: positive) return natural;
function size_to_width(x: positive) return positive;

constant NUM_INSTRUCTIONS: positive := 9;
constant INSTRUCTION_WIDTH: positive :=
size_to_width(NUM_INSTRUCTIONS);

function LOG2(x: positive) return natural is
variable x_temp: natural := 0;
variable count: natural := x/2;
begin
if x=0 then
assert (false)
report "LOG2: Invalid operation (x = 0)"
severity ERROR;
return 0;
end if;

while count/=0 loop
x_temp:=x_temp+1;
count := count/2;
end loop;
return x_temp;
end LOG2;

function size_to_width(x: positive) return positive is
begin
if x=1 then
return 1;
else
return (LOG2(x-1)+1);
end if;
end size_to_width;


In the design unit i write:

signal instruction: std_logic_vector(INSTRUCTION-WIDTH-1 downto 0);
...
with instruction select
temp <= "001" when INSTRUCTION_1, "010" when INSTRUCTION_2, ...,
"000" when others;

This code compiles with no errors in ActiveHDL 7.2
However it produces an error in Xilinx ISE 10.1:
ERROR:HDLParsers:839 - Selector (Signal 'instruction' of type
std_logic_vector) is an unconstrained array.

Well (what a surprise...) Xilinx has no further info on this error,
but I assume it has something to do with the expression not being
locally static.
The question is, how can i overcome this error in ISE without losing
the intended functionality?
Why does it compile without an error in ActiveHDL?

 

[Mike Treseler]

vxvoodoo@gmail.com wrote:

temp <= "001" when INSTRUCTION_1, "010" when INSTRUCTION_2, ...,
"000" when others;

This code compiles with no errors in ActiveHDL 7.2
However it produces an error in Xilinx ISE 10.1:
ERROR:HDLParsers:839 - Selector (Signal 'instruction' of type
std_logic_vector) is an unconstrained array.

Maybe temp is not constrained or
INSTRUCTION-WIDTH is not a constant
or xst is imperfect.

Signals and variables in synthesis code
must be a fixed length by elaboration time.
Constraints can come by declaring and using a subtype (recommended)
or anonymously, as in
std_logic_vector(INSTRUCTION-WIDTH-1 downto 0)
where INSTRUCTION-WIDTH is a constant.

Well (what a surprise...) Xilinx has no further info on this error,
but I assume it has something to do with the expression not being
locally static.

The device vendors know about transistor layout
not description languages.

The question is, how can i overcome this error in ISE without losing
the intended functionality?

Maybe use your function to declare a subtype length.

Why does it compile without an error in ActiveHDL?

Maybe the problem area is not elaborated in that case.

Here is a related function example.
See: function min_len_uns
http://mysite.verizon.net/miketreseler/min_vec_len.vhd

Good luck.

-- Mike Treseler

 

[Mike Treseler]

vxvoodoo@gmail.com wrote:

So the 'instruction' signal used as a selector is not locally static,
because its upper range boundary is calculated in a function. As a
result and as you correctly said, the signal is not fixed length
before elaboration time.

I think that's it.
Maybe use your function to declare a subtype length,
or use an 'if then elsif else' statement.

-- Mike Treseler

 

Maybe temp is not constrained or
INSTRUCTION-WIDTH is not a constant
or xst is imperfect.

Signals and variables in synthesis code
must be a fixed length by elaboration time.
Constraints can come by declaring and using a subtype (recommended)
or anonymously, as in
std_logic_vector(INSTRUCTION-WIDTH-1 downto 0)
where INSTRUCTION-WIDTH is a constant.

It seems that the problem lies in ActiveHDL and not in xst.
I replaced the "with...select" with a case statement and it generates
a compile error "Case expression must be of a locally static subtype",
which i believe should have generated for the "with...select"
statement as well, as i read in the comp.lang.vhdl FAQ
http://www.eda.org/comp.lang.vhdl/FAQ1.html#case

So the 'instruction' signal used as a selector is not locally static,
because its upper range boundary is calculated in a function. As a
result and as you correctly said, the signal is not fixed length
before elaboration time.
Thanks.