P
pico
Guest
Verilog-2001 adds constant functions
I try to call a constant expression for "Vector width declarations"
My code is below , but appear error message under ncverilog 05.00
Please help me to find where I make wrong
Thans~~~~
module c_t;
parameter size=8;
reg clk=0;
reg [clogb2(size)-1:0] count=0;
//reg [size-1:0] count=0;
initial begin
forever #1 clk=~clk;
end
always@(posedge clk)
count<=count+1;
function integer clogb2 ( input integer depth);
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth=depth>>>1;
end
endfunction
endmodule
I try to call a constant expression for "Vector width declarations"
My code is below , but appear error message under ncverilog 05.00
Please help me to find where I make wrong
Thans~~~~
module c_t;
parameter size=8;
reg clk=0;
reg [clogb2(size)-1:0] count=0;
//reg [size-1:0] count=0;
initial begin
forever #1 clk=~clk;
end
always@(posedge clk)
count<=count+1;
function integer clogb2 ( input integer depth);
begin
for(clogb2=0; depth>0; clogb2=clogb2+1)
depth=depth>>>1;
end
endfunction
endmodule