Const mul split to adder and shifter, how large number is op

[Yang Luo]

I have a test using 3277, it can split like this:
Info: 16 = 1 << 4
Info: 17 = 16 + 1
Info: 272 = 17 << 4
Info: 273 = 272 + 1
Info: 1092 = 273 << 2
Info: 819 = 1092 - 273
Info: 3276 = 819 << 2
Info: 3277 = 3276 + 1
I synthesis "module test_const_mul", it's combinational area is 88.
I synthesis "module test_const_mul_useadd", it's combinational area is 108.
So multiplication 3277 is not optimal splitting it. I know multiplication a constant less than 255 is optimal. Which number is the threshold?
module test_const_mul
#(
parameter WIDTH = 7
)
(
input i_clk ,//clock
input i_rst_n ,//reset
input [WIDTH-1:0] i_numWeghts ,
output [WIDTH+12-1:0] o_numBits
);
reg [WIDTH+11:0] r_numBits;
wire [WIDTH+11:0] w_numBits;
assign w_numBits = i_numWeghts * 3277;
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n) begin
r_numBits <= {(WIDTH+12){1'd0}};
end
else begin
r_numBits <= w_numBits;
end
end
assign o_numBits = r_numBits;
endmodule

module test_const_mul_useadd
#(
parameter WIDTH = 7
)
(
input i_clk ,//clock
input i_rst_n ,//reset
input [WIDTH-1:0] i_numWeghts ,
output [WIDTH+12-1:0] o_numBits
);
reg [WIDTH+11:0] r_numBits;
wire [WIDTH+9-1:0] w_numBits_t273;
assign w_numBits_t273 = (((i_numWeghts<<4)+i_numWeghts)<<4)+i_numWeghts;
wire [WIDTH+9+3-1:0] w_numBits_q2_t3277;
assign w_numBits_q2_t3277 = (((w_numBits_t273<<2)-w_numBits_t273)<<2)+i_numWeghts;
always @(posedge i_clk or negedge i_rst_n)
begin
if (!i_rst_n) begin
r_numBits <= {(WIDTH+12){1'd0}};
end
else begin
r_numBits <= w_numBits_q2_t3277;
end
end
assign o_numBits = r_numBits;
endmodule