Console I/O??

J

JT

Guest
I would like to have my testbench prompt the user to determine which
set of tests to run during a simulation. These tests would be
different tasks that would be called from this upper level testbench
user interface. The testbench would display a list of tests and their
associated numbers and then prompt for a test number to run. The
associated task would be executed and then control would return to
this upper level loop which would reprompt the user.

I've done this sort of thing in VHDL, and while system I/O isn't an
easy thing to do, it is possible. Is it possible to read from the
system input in verilog?

I've seen that its possible to do file writes to the system output
(from the verilog LRM) but is it possible to do file reads directed to
the system input?

Thx!
 
"JT" <jthibeault@yahoo.com> wrote in message
news:ea38511d.0311210642.766ab140@posting.google.com...

I would like to have my testbench prompt the user to determine which
set of tests to run during a simulation. These tests would be
different tasks that would be called from this upper level testbench
user interface. The testbench would display a list of tests and their
associated numbers and then prompt for a test number to run. The
associated task would be executed and then control would return to
this upper level loop which would reprompt the user.

I've done this sort of thing in VHDL, and while system I/O isn't an
easy thing to do, it is possible. Is it possible to read from the
system input in verilog?
Click to expand...
Not in Verilog-1995, no.

These are the practical possibilities I'm aware of:

1) Write a shell or Tcl script to launch your simulation. This
script can prompt the user for data, fabricate a suitable
(rather small!) readmemb file, and run the sim. Your
testbench then loads in the readmemb file, and gets your
user input that way.

2) As (1) above, but instead of creating a readmemb file,
set appropriate options to the simulator launch command.
These options might set a parameter on the top-level module,
or something similar. Details depend on your simulator.

3) Use a Verilog PLI application to give your running sim
access to file channels. The obvious place to go for this
is Chris Spear's excellent website
http://www.chris.spear.net/pli/fileio.htm

4) If you have a reasonably up-to-date simulator that supports
Verilog-2001 file constructs (recent versions of VCS, NCSim,
ModelSim) then you can use the new file mechanisms which
give you pretty much the same capability as C <stdio>.

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Thanks Jonathan!

Guess I'll check out the Verilog-2001 functions...


"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bpl920$i6u$1$830fa7a5@news.demon.co.uk>...
"JT" <jthibeault@yahoo.com> wrote in message
news:ea38511d.0311210642.766ab140@posting.google.com...

I would like to have my testbench prompt the user to determine which
set of tests to run during a simulation. These tests would be
different tasks that would be called from this upper level testbench
user interface. The testbench would display a list of tests and their
associated numbers and then prompt for a test number to run. The
associated task would be executed and then control would return to
this upper level loop which would reprompt the user.

I've done this sort of thing in VHDL, and while system I/O isn't an
easy thing to do, it is possible. Is it possible to read from the
system input in verilog?

Not in Verilog-1995, no.

These are the practical possibilities I'm aware of:

1) Write a shell or Tcl script to launch your simulation. This
script can prompt the user for data, fabricate a suitable
(rather small!) readmemb file, and run the sim. Your
testbench then loads in the readmemb file, and gets your
user input that way.

2) As (1) above, but instead of creating a readmemb file,
set appropriate options to the simulator launch command.
These options might set a parameter on the top-level module,
or something similar. Details depend on your simulator.

3) Use a Verilog PLI application to give your running sim
access to file channels. The obvious place to go for this
is Chris Spear's excellent website
http://www.chris.spear.net/pli/fileio.htm

4) If you have a reasonably up-to-date simulator that supports
Verilog-2001 file constructs (recent versions of VCS, NCSim,
ModelSim) then you can use the new file mechanisms which
give you pretty much the same capability as C <stdio>.

HTH
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
Please see implementation of "gets" function in Verilog PLI.
This function waits for user prompt and then assigns to Verilog
variable (integer or reg) the value entered by user.
Test.v illustrates how it works.

Regards,
Alexander Gnusin


------------------- gets.c-------------------------------------------

#include "veriuser.h" /* IEEE 1364 PLI TF routine library */
#include "acc_user.h" /* IEEE 1364 PLI ACC routine library */
#include <stdio.h>
#include <ctype.h>

/**********************************************************************
* calltf routine
*********************************************************************/
int gets_calltf()
{
char data[20];
gets(data);
tf_putp(0, atoi(data));
return(0);
}

------------------- EOF gets.c--------------------------------------


VCS tab file:
-------------------veriuser.tab (for VCS) -------------------------
$gets call=gets_calltf size=32 data=0
-------------------EOF veriuser.tab -------------------------------


MTI & Cadence veriuser.c file:
-------------------veriuser.c (MTI & Cadence)-----------------------
#include "veriuser.h"
#include "vxl_veriuser.h"

extern void gets_calltf();

s_tfcell veriusertfs[] = {
{userfunction, 0, 0, 0, gets_calltf, 0, "$gets"},
{ 0 } /* last entry must be 0 */
};

p_tfcell Bootstrap () {
return (veriusertfs);
}
-------------------EOF veriuser.c ----------------------------------



Verilog Example :
-------------------test.v-------------------------------------------

module test;
reg [0:31] a, b;
initial begin
$display("Enter value for a:");
a = $gets;
$display("Enter value for b:");
b = $gets;
#10 $display("a = %0d, b = %0d, sum = %0d", a, b, a+b);
$finish;
end
endmodule

-------------------EOF test.v---------------------------------------

Run commands:

gcc -I<vcs_or_ncv_path>/include/ -c gets.c -o gets.o

#Synopsys VCS:
vcs -R test.v -P veriuser.tab gets.o

#Cadence NC Verilog:
gcc veriuser.c -c -I<ncv_path>/include -o veriuser.o
ld -G veriuser.o gets.o -o libpli.so
setenv LD_LIBRARY_PATH .:$LD_LIBRARY_PATH
ncverilog test.v
 
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