Connecting std_ulogic_vector to std_logic_vector

[Roel]

Hi

A bi-directional bus from type std_ulogic_vector (from a model from
fmf) has to be connected to a bidirectional bus from type
std_logic_vector. I created a type-conversion block for the conversion
but the simulator/compiler keeps complaining: multiple driver.

ENTITY:

data : inout std_logic_vector(31 downto 0);
udata : inout std_ulogic_vector(31 downto 0);

ARCHITECTURE:

data <= to_stdlogicvector(udata);
udata <= to_stdulogicvector(data);

How should I implement a kind of RESOLVE function to go from one type
to another?

Thank you,

Roel

 

[Egbert Molenkamp]

"Roel" <electronics_designer@hotmail.com> schreef in bericht
news:69abd80a.0401300136.61b6aac9@posting.google.com...

Hi

A bi-directional bus from type std_ulogic_vector (from a model from
fmf) has to be connected to a bidirectional bus from type
std_logic_vector. I created a type-conversion block for the conversion
but the simulator/compiler keeps complaining: multiple driver.

I don't know which model you are trying to use. But if the inout port is
of type std_Ulogic_vector (which is un unresolved type) it will be rather
difficult to solve your problem. I would expect that if it is was really
the intention of the model to use it as a bidirectional bus that the type
should be std_logic_vector.
(It could be that the designer of the model uses INOUT because an
output signal of the model is also internally needed.)

Egbert Molenkamp

 

[Roel]

"Egbert Molenkamp" <molenkam_no_spam@cs.utwente.nl> wrote in message news:<bvg5vi$mfv$1@ares.cs.utwente.nl>...

"Roel" <electronics_designer@hotmail.com> schreef in bericht
news:69abd80a.0401300136.61b6aac9@posting.google.com...
Hi

A bi-directional bus from type std_ulogic_vector (from a model from
fmf) has to be connected to a bidirectional bus from type
std_logic_vector. I created a type-conversion block for the conversion
but the simulator/compiler keeps complaining: multiple driver.

I don't know which model you are trying to use. But if the inout port is
of type std_Ulogic_vector (which is un unresolved type) it will be rather
difficult to solve your problem. I would expect that if it is was really
the intention of the model to use it as a bidirectional bus that the type
should be std_logic_vector.
(It could be that the designer of the model uses INOUT because an
output signal of the model is also internally needed.)

Egbert Molenkamp

The model I'm usign is the
http://www.eda.org/fmf/fmf_public_models/flash/am29lv512n.vhd

All the signals of the DQ bus are INOUT and of std_ulogic. The signals
should be bidirectional, you should read and write to the model.

Is it not possible to interface this in some way to std_logic INOUT
signals?

Best regards,
Roel

 

[Mike Treseler]

Roel wrote:

A bi-directional bus from type std_ulogic_vector (from a model from
fmf) has to be connected to a bidirectional bus from type
std_logic_vector. I created a type-conversion block for the conversion
but the simulator/compiler keeps complaining: multiple driver.

I don't know which model you are trying to use. But if the inout port is
of type std_Ulogic_vector (which is un unresolved type) it will be rather
difficult to solve your problem. I would expect that if it is was really
the intention of the model to use it as a bidirectional bus that the type
should be std_logic_vector.
(It could be that the designer of the model uses INOUT because an
output signal of the model is also internally needed.)

Egbert Molenkamp


The model I'm usign is the
http://www.eda.org/fmf/fmf_public_models/flash/am29lv512n.vhd

All the signals of the DQ bus are INOUT and of std_ulogic. The signals
should be bidirectional, you should read and write to the model.

Is it not possible to interface this in some way to std_logic INOUT
signals?

It is possible since the std_ulogic bit type of the model is directly
compatible with std_logic.

You could instance am29lv512n.vhd in your test bench
something like the example below.


-- Mike Treseler


architecture sim of test_AM29LV512N is

-- component generics
constant tipd_A0 : VitalDelayType01 := VitalZeroDelay01;
constant tipd_A1 : VitalDelayType01 := VitalZeroDelay01;
-- etc. etc.

-- component ports
signal A24_s : std_ulogic := 'U'; -- [IN]
signal A23_s : std_ulogic := 'U'; -- [IN]
-- etc. etc.
signal A0_s : std_ulogic := 'U'; -- [IN]

signal DQ15_s : std_ulogic := 'U'; -- [INOUT]
-- etc etc
signal DQ0_s : std_ulogic := 'U'; -- [INOUT]
signal CENeg_s : std_ulogic := 'U'; -- [IN]
signal OENeg_s : std_ulogic := 'U'; -- [IN]
signal WENeg_s : std_ulogic := 'U'; -- [IN]
signal RESETNeg_s : std_ulogic := 'U'; -- [IN]
signal WPNeg_s : std_ulogic := 'U'; -- [IN]
signal BYTENeg_s : std_ulogic := 'U'; -- [IN]
signal RY_s : std_ulogic := 'U'; -- [OUT]

signal tb_dbus : std_logic_vector(15 downto 0); -- my testbench signal
-- resolved type
begin -- architecture sim

-- model instantiation
DUT: entity work.AM29LV512N
generic map (tipd_A0 => tipd_A0,
tipd_A1 => tipd_A1,
-- etc. etc.
LongTimming => LongTimming,
TimingModel => TimingModel)

port map (A24 => A24_s, -- [IN]
-- etc. etc.
A0 => A0_s, -- [IN]

DQ15 => DQ15_s, -- [INOUT]
-- etc. etc.
DQ0 => DQ0_s, -- [INOUT]

CENeg => CENeg_s, -- [IN]
OENeg => OENeg_s, -- [IN]
WENeg => WENeg_s, -- [IN]
RESETNeg => RESETNeg_s, -- [IN]
WPNeg => WPNeg_s, -- [IN]
BYTENeg => BYTENeg_s, -- [IN]
RY => RY_s); -- [OUT]


tb_dbus <= (

DQ15_s,
DQ14_s,
DQ13_s,
DQ12_s,
DQ11_s,
DQ10_s,
DQ9_s,
DQ8_s,
DQ7_s,
DQ6_s,
DQ5_s,
DQ4_s,
DQ3_s,
DQ2_s,
DQ1_s,
DQ0_s); -- bus to model

tb_dbus <= (tb_dbus'range => 'Z'); -- bus to testbench etc. etc.





end architecture sim;