Connecting seperate substrate nets on extracted and schemati

Hi all,

I am using a flow which includes Diva LVS, but because my layouts and
schematics use different grounds (gnd! and gnda!) the LVS gets upset
about the substrate being connected to different nets. I have to create
a special LVS version of my schematic and layout and ensure that there
is only one net connected to the substrate (i.e. either gnd! or gnda!).
This is a pain to do and it would be great if I could write a script to
search the extracted view (is it just a netlist?) and replace any
occurrences of gnda! with gnd!. I would also like to be able to do this
with the schematic, but I guess it would have to be easy to change it
back after the LVS...

Any ideas or suggestions welcome.

Also did anyone ever manage to get remote simulation in analog artist
working on a machine which requires a username/password? I need some
way of auto signing into the machine without requiring a password - I
can do this with ssh but I think the remote simulation uses rsh?

Cheers,

Reuben

 

Bernd,

Sorry, I must have not been clear - both the schematic and layout are
identical - both have both gnd! and gnda! in various places to seperate
digital and analogue functionality. So, the LVS should work as they
*are* identical. However, it appears that it gets confused because it
assumes one net for the whole substrate so having two net names on
there throws up (incorrect) mismatches. All I want to do is to
temporarily change *both* the layout and schematic so that all the
gnda! nets (in both the layout and schematic) are renamed gnd! just for
the LVS. Of course at a higher level (e.g. testbench circuit) the gnda!
and gnd! are connected (through a tiny resistor for example) but I need
to keep them as seperate nets becuase they will be connected to two
different pins on the chip (for noise reasons).

Hope that makes sense. I shall look at inherited nets - I never really
understood exactly how they functioned.

Cheers,

Reuben

 

[fogh]

Reuben,

It seems you want gnda! and gnd! to be connected through p-epi only, so your
LVS check should flag when you have connected them through metal. Right ?

Then you need to partition your substrate as Reuben explained already,

bg = geomBkgnd( )
PTsub1 = geomSize( PTsub 0.001)
PTsub2 = geomAndNot( PTsub1 PTsub) ; make a ring that is thinner than
any connection overlap.
pepi = geomAndNot( bg PTsub2 ) ; partition the epi
PTpwell = geomAnd( pwell pepi ) ; partition of pwell

.... and also connect the partitions

stamp_psub = geomStamp( pepi PTpwell )

If you don t have something like that in your PDK already, you need to add
this to divaEXT.rul /assura extract.rul , and of course add the layer PTsub to
your techfile and display.

Bernd Fischer > wrote:

Reuben,

Hope that makes sense. I shall look at inherited nets - I never really
understood exactly how they functioned.

I think inherited connection will then not help here to solve the LVS
issue.
But you can find a good app not here:
http://sourcelink.cadence.com/en/infomgmt/AppNoteResult.jhtml?product=Composer&displayname=Virtuoso+Composer


I most of the design kits I have seen, there is a dummy layer
to separate substrate if you have more than one net connected
to it in layout, for LVS purpose.

The Diva rule file should then look similar to this, somewhere at the
top:

;; derive Substrate
bulk = geomBkgnd()
psub = geomAndNot( bulk nwell )
psub2_up_03 = geomSize( psub2 .03 )
psub_temp_a = geomAndNot( psub psub2_up_03 )
psub_temp_b = geomAnd( psub psub2 )
psub = geomOr( psub_temp_a psub_temp_b )

where pusb2 is the dummy layer to separate the substrate.
psub2 = geomOr( "PSUB2" )


If you follow your idea,
the problem of a change to one common ground node is
to remember where and what the old values for the nets have been.
No mater if you change them manually or over a user interface
or over a script.
You have to have anyhow two cellview pairs for LVS and one
for real live I guess.


Bernd



reubenwilcock@hotmail.com wrote:

Bernd,

Sorry, I must have not been clear - both the schematic and layout are
identical - both have both gnd! and gnda! in various places to seperate
digital and analogue functionality. So, the LVS should work as they
*are* identical. However, it appears that it gets confused because it
assumes one net for the whole substrate so having two net names on
there throws up (incorrect) mismatches. All I want to do is to
temporarily change *both* the layout and schematic so that all the
gnda! nets (in both the layout and schematic) are renamed gnd! just for
the LVS. Of course at a higher level (e.g. testbench circuit) the gnda!
and gnd! are connected (through a tiny resistor for example) but I need
to keep them as seperate nets becuase they will be connected to two
different pins on the chip (for noise reasons).

Hope that makes sense. I shall look at inherited nets - I never really
understood exactly how they functioned.
Cheers,

Reuben