connecting modules

[RI]

Hi all,
I am a novice Verilog user. I want to connect two modules, to pass the
2 bits wide quad generated in module aaa to tie to module bbb. However
I do not need quad in the top module.
My kludge is not working. What's the correct way?

module aaa (clock,quad);
input clock;
output reg [1:0]quad;
//code
endmodule

module bbb (clock,quad,foo);
input clock;
input [1:0]quad;
output foo;
//code
endmodule

module top(CLOCK,FOO)
input clock;
output foo;
aaa aa(CLOCK,quad);
bbb bb(CLOCK,quad,FOO);
wire [1:0]quad;
endmodule

Istvan

 

[Explorer]

There are couple of problems in top module (in the pasted code)
I have put down the description below

Issue 1:
---------
module top(CLOCK,FOO)
should be
module top(CLOCK,FOO);


Issue 2:
---------
input clock;
should be
input CLOCK;

Issue 3:
---------
output foo;
should be
output FOO;

Issue 4: (actual issue with your code)
wire [1:0]quad;
should be moved above the instantiations. if you dont declare a wire
and use it in instantiations, then verilog creates a single bit wide
wire automatically. The declaration afterwards is ignored.

Your Final Code:
module top(CLOCK,FOO);
input CLOCK;
output FOO;
wire [1:0]quad;
aaa aa(CLOCK,quad);
bbb bb(CLOCK,quad,FOO);
endmodule

 

[gabor]

On Feb 20, 10:06 am, Explorer <tarun.b...@gmail.com> wrote:

There are couple of problems in top module (in the pasted code)
I have put down the description below

Issue 1:
---------
module top(CLOCK,FOO)
should be
module top(CLOCK,FOO);

Issue 2:
---------
input clock;
should be
input CLOCK;

Issue 3:
---------
output foo;
should be
output FOO;

Issue 4: (actual issue with your code)
wire [1:0]quad;
should be moved above the  instantiations. if you dont declare a wire
and use it in instantiations, then verilog creates a single bit wide
wire automatically. The declaration afterwards is ignored.

[snip]

Actually I would expect an error message such as:
"Illegal re-declaration of quad at line xxx"

This hints at the implicit declaration of "quad"
in the first module instantiation port list.

For Verilog 2001 you can use the `default_nettype none
directive to force the error message at the first
attempt to use "quad", instead. This would also
catch the case where you didn't subsequently try to
define quad as a vector.

Regards,
Gabor

 

[Explorer]

On Feb 20, 11:09 am, gabor <ga...@alacron.com> wrote:

On Feb 20, 10:06 am, Explorer <tarun.b...@gmail.com> wrote:

There are couple of problems in top module (in the pasted code)
I have put down the description below

Issue 1:
---------
module top(CLOCK,FOO)
should be
module top(CLOCK,FOO);

Issue 2:
---------
input clock;
should be
input CLOCK;

Issue 3:
---------
output foo;
should be
output FOO;

Issue 4: (actual issue with your code)
wire [1:0]quad;
should be moved above the  instantiations. if you dont declare a wire
and use it in instantiations, then verilog creates a single bit wide
wire automatically. The declaration afterwards is ignored.

[snip]

Actually I would expect an error message such as:
"Illegal re-declaration of quad at line xxx"

This hints at the implicit declaration of "quad"
in the first module instantiation port list.

For Verilog 2001 you can use the `default_nettype none
directive to force the error message at the first
attempt to use "quad", instead.  This would also
catch the case where you didn't subsequently try to
define quad as a vector.

Regards,
Gabor

Well most of the standard simulators will issue you a a warning (not
an error) pointing out the redeclaration ignored.
`default_nettype is undoubtedly good thing to use if the design/
verification engineer wants to avoid implicit interpretations.
regards.
explorer

 

[RI]

Hi guys,
thank for your help. Actually I didn't miss as much errors as it
seems, but wanted to shrink my question to minimum. So I created these
lines 'on the fly'. It resulted missing semicolons...
Actually my question was answered, thank to you, the key was moving
the wire declaration above.
Thanks again,
Istvan
Gabor, this is the second beer