Connect SystemVerilog interface to Verilog module ?

D

Davy

Guest
Hi,

I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional
Verilog module? Can I both use modport and instance the module? Or is
there any walk around method? Thanks!

//----- Verilog Module-----
module dut(
CLK,
RESET,
DATA,
... ...
);
input CLK, RESET;
output DATA;
....
//-----------------------------------

and
//----- SystemVerilog Interface-----
interface dut_tb_if;
bit clk,reset,data;

modport... ...
//---------------------------------------------

Best regards,
Davy
 
Davy,

define an interface:

interface a_name
(
input logic clk
) ;

timeunit 1ns;
timeprecision 1ns;

logic [7:0] data ;
logic reset;

modport dut_verilog (input reset, input data ) ;
modport test_systemverilog (output reset, output data ) ;

endinterface : a_name

In the dut use it as:
module dut_verilog
(
input logic clk ,
a_name interface_name
) ;

In the test use it as
module test_system_verilog
(
input logic clk , // from top
a_name interface_name
) ;

this should get you going in the right direction!

Macgyver

On Nov 28, 3:17 am, "Davy" <zhushe...@gmail.com> wrote:
Hi,

I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional
Verilog module? Can I both use modport and instance the module? Or is
there any walk around method? Thanks!

//----- Verilog Module-----
module dut(
CLK,
RESET,
DATA,
... ...
);
input CLK, RESET;
output DATA;
...
//-----------------------------------

and
//----- SystemVerilog Interface-----
interface dut_tb_if;
bit clk,reset,data;

modport... ...
//---------------------------------------------

Best regards,
Davy
 
Hi Sharp,

Yes, I use the method you mention and it pass, thanks!

Best regards,
Davy

sharp@cadence.com wrote:
Davy wrote:
Hi,

I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional
Verilog module? Can I both use modport and instance the module? Or is
there any walk around method? Thanks!

//----- Verilog Module-----
module dut(
CLK,
RESET,
DATA,
... ...
);
input CLK, RESET;
output DATA;
...
//-----------------------------------

and
//----- SystemVerilog Interface-----
interface dut_tb_if;
bit clk,reset,data;

modport... ...
//---------------------------------------------

If the dut really has to be pure Verilog, then you will have to attach
the signals from the interface individually to the dut. For example

dut d1(.CLK(iface.clk), .RESET(iface.reset), .DATA(iface.data));
 
Davy wrote:
Hi,

I want to write SystemVerilog testbench for traditional Verilog module.
But I have no idea how to SystemVerilog interface to traditional
Verilog module? Can I both use modport and instance the module? Or is
there any walk around method? Thanks!

//----- Verilog Module-----
module dut(
CLK,
RESET,
DATA,
... ...
);
input CLK, RESET;
output DATA;
...
//-----------------------------------

and
//----- SystemVerilog Interface-----
interface dut_tb_if;
bit clk,reset,data;

modport... ...
//---------------------------------------------
If the dut really has to be pure Verilog, then you will have to attach
the signals from the interface individually to the dut. For example

dut d1(.CLK(iface.clk), .RESET(iface.reset), .DATA(iface.data));
 

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