Confused with syntax

[Daku]

Could some Verilog guru please clarify a small thing ? Recently, while
going over some RTL code I saw:
dff #(1) d0_0 (
..l1clk(l1clk),
..siclk(siclk),
..soclk(soclk),
..d(fdin[0:0]),
..si(scan_in),
..so(scan_out),
..q(dout[0:0])
);

May I know what the "#(1)" is supposed to mean, in this context,
i.e., instantiating a dff ?
Any hints, suggestions would be of immense help. Thanks in
advance.

 

[Jonathan Bromley]

On Sun, 8 May 2011 20:25:45 -0700 (PDT), Daku <dakupoto@gmail.com>
wrote:

Could some Verilog guru please clarify a small thing ? Recently, while
going over some RTL code I saw:
dff #(1) d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);

May I know what the "#(1)" is supposed to mean, in this context,
i.e., instantiating a dff ?
Any hints, suggestions would be of immense help. Thanks in
advance.

hi Daku,

It's just a parameter override. Presumably module dff looks
something like this:

module dff #(parameter n_bits = 8)
(input llclk, .... );

And when you create your instance d0_0 of dff, you need
to set the parameter "n_bits" to the value 1.

Modern versions of Verilog allow you to do named parameter
mapping as well as port mapping, so you could have this:

dff #(.n_bits(1)) d0_0(...);

Anyway, look up "module parameters" in whatever texts you have,
to find out more details.
--
Jonathan Bromley