S
Stefan Joeres
Guest
Hi altogether,
our university is dealing with different Design Kits from industry partners
(e.g. ST, Infineon, Atmel,...). The setup for each Project is done by the
use of the module-package for linux (FC 4).
Actually we're getting more and more confused from the setups of the current
IC, IUS and MMSIM releases.
Can you state and explain your individual setup of
Environment Variables ( CDSHOME, CDS_INST_DIR, IC_INST_DIR,
CDS_Netlisting_Mode, PATH & LD_LIBRARY_PATH,...)
and your settings for the cds.lib (and hdl.var if necessary) ?
Desired releases here would be IC 5.10.41.USR4, MMSIM 61 & 60, IUS 54 to
58.2P2, ASSURA 3.14
The target applications include
transistor level design & layout of mixed signal ICs
behavioural modelling using SysVerilog, VAMS, VHDL and matlab/simulink
coupling.
Maybe there's a good howto on the setup ? The documentation from cadence
itself typically doesn't cover the combination of the different tools (at
least as far as I've found them ...) .
Regards,
Stefan Joeres
our university is dealing with different Design Kits from industry partners
(e.g. ST, Infineon, Atmel,...). The setup for each Project is done by the
use of the module-package for linux (FC 4).
Actually we're getting more and more confused from the setups of the current
IC, IUS and MMSIM releases.
Can you state and explain your individual setup of
Environment Variables ( CDSHOME, CDS_INST_DIR, IC_INST_DIR,
CDS_Netlisting_Mode, PATH & LD_LIBRARY_PATH,...)
and your settings for the cds.lib (and hdl.var if necessary) ?
Desired releases here would be IC 5.10.41.USR4, MMSIM 61 & 60, IUS 54 to
58.2P2, ASSURA 3.14
The target applications include
transistor level design & layout of mixed signal ICs
behavioural modelling using SysVerilog, VAMS, VHDL and matlab/simulink
coupling.
Maybe there's a good howto on the setup ? The documentation from cadence
itself typically doesn't cover the combination of the different tools (at
least as far as I've found them ...) .
Regards,
Stefan Joeres