Confused by negedge

Hey all,

I'm new at Verilog and I thought I would try something simple to learn
the basics. I am trying to hook up a NES controller to my FPGA devkit,
but I'm having a bit of difficulty with the code.

The waveform for NES controllers can be seen here:
http://seb.riot.org/nescontr/controller-read.png

My problem is that you are supposed to read the button data on the
negative edge of the clock or latch, but since it is the negative
edge, I cannot work out how to find which line was clocked. My code is
as follows (note: I know this code does not work):

module decoder(latch,
clock,
data,
decoded
);
output [7:0] decoded; // For the final data
input latch;
input clock;
input data;
reg [7:0] decoded; // Final decoded output
integer counter; // Count the number of clocks
assign temp = (counter < 7); // Xilinx says: "Perform your
combinatorial logic outside always blocks!"
always @ (negedge clock or negedge latch) begin // Whenever there is a
latch or clock, do something on the negative edge
if (latch) begin // If it was a latch signal (this is broken)
decoded[0] <= data; // Store the first button
end
if (clock) begin // If it was a clock (this is broken too)
decoded[counter] <= data; // Record the button
if (temp) begin // If the counter is still in range
counter <= counter + 1; // Increment
end else begin // If the counter is on the end of the range
counter <= 1; // Reset it
end
end
end
endmodule

If anyone has any ideas on how I could solve this problem, it would be
much appreciated.

Thanks in advance,
penjuin

 

[mk]

On Tue, 5 Feb 2008 00:10:14 -0800 (PST), penjuin@gmail.com wrote:

Hey all,

The waveform for NES controllers can be seen here:
http://seb.riot.org/nescontr/controller-read.png

My problem is that you are supposed to read the button data on the
negative edge of the clock or latch, but since it is the negative
edge, I cannot work out how to find which line was clocked. My code is
as follows (note: I know this code does not work):

In general you may not have multiple edged events controlling an
always block. You need to decide what's your clock and use everything
else as an event which you sample with your clock. If the waveform is
indeed accurate it's not feasible to use either signal as a clock
easily. What you can do is to use a much faster clock and sample both
latch and "clock" signals and decide which event has happened. Suppose
you have a clock which has a period of 1/10 of either latch width or
"clock" width. Then you can use something like this:

always @(posedge clk) //use a high speed posedge clock
begin
clockd1 <=clock;
clockd2 <=clockd1;
clockd3 <=clockd2;
latchd1 <= latch;
latchd2 <= latchd1;
latchd3 <= latchd2;

if (latchd3 & !latchd2) // detecte negedge of latch
...

if (clockd3 & !clockd2) // detect negedge of "clock"
...
end

on the other hand if latch is a signal synchronous to "clock" and
overlaps clock you can say

always (negedge clock)
begin
// if we're here negedge of clock has happened
if (!latch) // if latch is zero
...
end

Hth.

 

[mk]

On Tue, 5 Feb 2008 00:10:14 -0800 (PST), penjuin@gmail.com wrote:

Hey all,

I'm new at Verilog and I thought I would try something simple to learn
the basics. I am trying to hook up a NES controller to my FPGA devkit,
but I'm having a bit of difficulty with the code.

The waveform for NES controllers can be seen here:
http://seb.riot.org/nescontr/controller-read.png

Actually the following page is a much clearer place to understand
what's needed. It turns out latch & clock are generated by the host
(ie you) and the data is driven by data controller. So the host block
which needs to receive the data doesn't need to be concerned about the
latch signal at all. All it needs to see is that clock signal which
goes out and the data signal which comes in serially.
http://users.ece.gatech.edu/~hamblen/489X/f04proj/USB_NES/protocol.htm

 

On Feb 5, 6:39 pm, mk <kal*@dspia.*comdelete> wrote:

On Tue, 5 Feb 2008 00:10:14 -0800 (PST), penj...@gmail.com wrote:
Hey all,

I'm new at Verilog and I thought I would try something simple to learn
the basics. I am trying to hook up a NES controller to my FPGA devkit,
but I'm having a bit of difficulty with the code.

The waveform for NES controllers can be seen here:
http://seb.riot.org/nescontr/controller-read.png

Actually the following page is a much clearer place to understand
what's needed. It turns out latch & clock are generated by the host
(ie you) and the data is driven by data controller. So the host block
which needs to receive the data doesn't need to be concerned about the
latch signal at all. All it needs to see is that clock signal which
goes out and the data signal which comes in serially.http://users.ece.gatech.edu/~hamblen/489X/f04proj/USB_NES/protocol.htm

Wow, thanks for picking up on my mistake mk. I should have done more
research :$. At least know I know how to do it now!