Configuring Altera FLEX10KE using EPC2 device

[Dimitris Kontodimopoulos]

Hello there

I'm having serious problems configuring my FPGA using EPC2. We have
designed the circuit exactly as stated in the Altera datasheet and
even played around with the pullups and buffering that's recommended.
To be more specific, We have a board with a FLEX10KE
(EPF10K200SBC356-1) and a EPC2LC20 for in-system configuration. We
also have provided for direct Byteblaster configuration using a
connector (using the same path towards the FPGA and selecting between
them through enabling/disabling a buffer). Finally, we have a JTAG
connector by which we can configure the FPGA directly using the SOF
file generated by Quartus - pls read below.
Anyway, what we're seeing is:
The EPC2 gets progammed OK but then the problems start. When I turn
the system off and on again to initiate configuration the nCONFIG pin
comes out of reset and so does nSTATUS but only for a very small
amount of time. During this time DCLK goes enabled and DATA transfers
configuration data, as normally. Then nSTATUS goes low again and the
configuration is interrupted as you would expect. There is nothing in
the circuit that could pull this pin low - it is a point to point
connection between FPGA and EPC2. It seems however that the EPC2 goes
back on reset state hence pulling its OE pin low. From that point
onwards these signals are going crazy, ie they randomly go high or low
so the FPGA never gets configured. Tried using external pullups whilst
disabling the internal ones through Quartus, but there was no change.
One last point is that so far I've been configuring the FPGA through a
direct JTAG connection using the SOF file - this works fine. Does this
perhaps confuse the device, ie how does it know whether it should be
programmed through JTAG or EPC2. Do I need to set something there?
Finally, I'm using the POF file to program the EPC2 - I'm assuming
this is correct?? Please give me some feedback because I'm really
stuck with this. Any tips would be much welcome. Thanks in advance

 

[Rene Tschaggelar]

Dimitris Kontodimopoulos wrote:

Hello there

I'm having serious problems configuring my FPGA using EPC2. We have
designed the circuit exactly as stated in the Altera datasheet and
even played around with the pullups and buffering that's recommended.
To be more specific, We have a board with a FLEX10KE
(EPF10K200SBC356-1) and a EPC2LC20 for in-system configuration. We
also have provided for direct Byteblaster configuration using a
connector (using the same path towards the FPGA and selecting between
them through enabling/disabling a buffer). Finally, we have a JTAG
connector by which we can configure the FPGA directly using the SOF
file generated by Quartus - pls read below.
Anyway, what we're seeing is:
The EPC2 gets progammed OK but then the problems start. When I turn
the system off and on again to initiate configuration the nCONFIG pin
comes out of reset and so does nSTATUS but only for a very small
amount of time. During this time DCLK goes enabled and DATA transfers
configuration data, as normally. Then nSTATUS goes low again and the
configuration is interrupted as you would expect. There is nothing in
the circuit that could pull this pin low - it is a point to point
connection between FPGA and EPC2. It seems however that the EPC2 goes
back on reset state hence pulling its OE pin low. From that point
onwards these signals are going crazy, ie they randomly go high or low
so the FPGA never gets configured. Tried using external pullups whilst
disabling the internal ones through Quartus, but there was no change.
One last point is that so far I've been configuring the FPGA through a
direct JTAG connection using the SOF file - this works fine. Does this
perhaps confuse the device, ie how does it know whether it should be
programmed through JTAG or EPC2. Do I need to set something there?
Finally, I'm using the POF file to program the EPC2 - I'm assuming
this is correct?? Please give me some feedback because I'm really
stuck with this. Any tips would be much welcome. Thanks in advance

is your setup
able to program both, FPGA and EPC2 through JTAG ?

Yes, a pullup on TMS, TDI and a pulldown on TCK. AN116 shows
all that nicely. Yes, SOF for the RAM, POF for the EEPROM parts.
The pullup and pulldown make the control lines to have the right
state such that the FPGA is loaded from the EPC2 at powerup.

Then the reportfile *.rpt gives an assumed pin useage, especially
for those pin you did not use. I also recently learnt that there may
not be any open inputs on certain families.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Greg Steinke]

dkonto@isd.gr (Dimitris Kontodimopoulos) wrote in message news:<1609ee5e.0403010148.1b9c61df@posting.google.com>...

Hello there

I'm having serious problems configuring my FPGA using EPC2. We have
designed the circuit exactly as stated in the Altera datasheet and
even played around with the pullups and buffering that's recommended.
To be more specific, We have a board with a FLEX10KE
(EPF10K200SBC356-1) and a EPC2LC20 for in-system configuration. We
also have provided for direct Byteblaster configuration using a
connector (using the same path towards the FPGA and selecting between
them through enabling/disabling a buffer). Finally, we have a JTAG
connector by which we can configure the FPGA directly using the SOF
file generated by Quartus - pls read below.
Anyway, what we're seeing is:
The EPC2 gets progammed OK but then the problems start. When I turn
the system off and on again to initiate configuration the nCONFIG pin
comes out of reset and so does nSTATUS but only for a very small
amount of time. During this time DCLK goes enabled and DATA transfers
configuration data, as normally. Then nSTATUS goes low again and the
configuration is interrupted as you would expect. There is nothing in
the circuit that could pull this pin low - it is a point to point
connection between FPGA and EPC2. It seems however that the EPC2 goes
back on reset state hence pulling its OE pin low. From that point
onwards these signals are going crazy, ie they randomly go high or low
so the FPGA never gets configured. Tried using external pullups whilst
disabling the internal ones through Quartus, but there was no change.
One last point is that so far I've been configuring the FPGA through a
direct JTAG connection using the SOF file - this works fine. Does this
perhaps confuse the device, ie how does it know whether it should be
programmed through JTAG or EPC2. Do I need to set something there?
Finally, I'm using the POF file to program the EPC2 - I'm assuming
this is correct?? Please give me some feedback because I'm really
stuck with this. Any tips would be much welcome. Thanks in advance

Hi Dimitris,

Generally, when nSTATUS goes low, it is because the FPGA has seen
corrupted data. It knows this because each frame of data has a
checksum, so if the frame is corrupted the computed and transmitted
checksum don't match. The most common cause of corrupted data is
double-clocking on DCLK. So the first thing I suggest is to monitor
DCLK, as close as possible to the device. You are in a BGA, so the
best would be to probe under the board. If you have noise on DCLK,
this can show up as double clocking. Your buffer may have fast
drivers, and that's not always good - an unterminated line driven by a
fast-switching driver can exhibit ringing which will cause clocking
problems.

Another possibility is that the connection through the buffer is
causing a problem with the DCLK vs DATA timing. This is unlikely but
possible - imagine that DCLK is shifted vs DATA, then the tSU and tH
may not be met. So you can check that as well.

For the specific question about JTAG: you select which configuration
mode you want by setting the MSEL pins. The JTAG config works for any
valid combination of MSEL pins. When the FPGA sees the JTAG "config"
instruction coming in on TDI and TCK it then starts to configure by
JTAG. You probably have the MSEL pins set correctly since
configuration begins correctly - but it's worth a check.

Altera has developed a Configuration Troubleshooter to help debug
configuration issues. It's on
http://www.altera.com/cgi-bin/ts.pl?fn=configuration

I encourage you to give it a try, as this can solve most configuration
issues, and it's open 24/7!

Sincerely,
Greg Steinke
gregs@altera.com
Altera Corporation

 

[ron proveniers]

HI there.


Did you look at power supply.
During configuration the FPGA draws a lot of power ( can be > 500Ma!!).
If PSU can not deliver this, you have aconfiguration problem.

success

ron proveniers



"Dimitris Kontodimopoulos" <dkonto@isd.gr> schreef in bericht
news:1609ee5e.0403010148.1b9c61df@posting.google.com...

Hello there

I'm having serious problems configuring my FPGA using EPC2. We have
designed the circuit exactly as stated in the Altera datasheet and
even played around with the pullups and buffering that's recommended.
To be more specific, We have a board with a FLEX10KE
(EPF10K200SBC356-1) and a EPC2LC20 for in-system configuration. We
also have provided for direct Byteblaster configuration using a
connector (using the same path towards the FPGA and selecting between
them through enabling/disabling a buffer). Finally, we have a JTAG
connector by which we can configure the FPGA directly using the SOF
file generated by Quartus - pls read below.
Anyway, what we're seeing is:
The EPC2 gets progammed OK but then the problems start. When I turn
the system off and on again to initiate configuration the nCONFIG pin
comes out of reset and so does nSTATUS but only for a very small
amount of time. During this time DCLK goes enabled and DATA transfers
configuration data, as normally. Then nSTATUS goes low again and the
configuration is interrupted as you would expect. There is nothing in
the circuit that could pull this pin low - it is a point to point
connection between FPGA and EPC2. It seems however that the EPC2 goes
back on reset state hence pulling its OE pin low. From that point
onwards these signals are going crazy, ie they randomly go high or low
so the FPGA never gets configured. Tried using external pullups whilst
disabling the internal ones through Quartus, but there was no change.
One last point is that so far I've been configuring the FPGA through a
direct JTAG connection using the SOF file - this works fine. Does this
perhaps confuse the device, ie how does it know whether it should be
programmed through JTAG or EPC2. Do I need to set something there?
Finally, I'm using the POF file to program the EPC2 - I'm assuming
this is correct?? Please give me some feedback because I'm really
stuck with this. Any tips would be much welcome. Thanks in advance