Configuration for mixed mode vhdl / Verilog

[Rakesh YC]

Hi All
My problem is I'd like to choose VHDL entity instantiated in verilog module
via a VHDL configuration

To summerize: I have a hierarcy "top:vhdl - verilog - verilog - vhdl:bottom"
structure. How to write a vhdl configuration to select the file for the bottom
instantiation?

If such vhdl configuration type is not possible, any suggestions to solve
this?

Rakesh YC

 

[Just an Illusion]

Hi Rakesh,

See thread 'mixed Verilog/VHDL design' from botao.
You can find some possible solutions.

JaI

Rakesh YC wrote:

Hi All
My problem is I'd like to choose VHDL entity instantiated in verilog module
via a VHDL configuration

To summerize: I have a hierarcy "top:vhdl - verilog - verilog - vhdl:bottom"
structure. How to write a vhdl configuration to select the file for the bottom
instantiation?

If such vhdl configuration type is not possible, any suggestions to solve
this?

Rakesh YC