configuration error

[srinukasam]

Hello
I designed one simple mux , then I instantiated the basic mux with
generate loop for more outputs.while compiling with model sim its giving
error as
Error: ..component instance mux1:mux not found.
Is the problem with configuration statement or any others..
Please help me
thank you

DESIGN:used as a component --------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux is
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector (input_w-1 downto 0);
ctrl: in std_logic_vector (ictrl_w-1 downto 0);
out_muxut std_logic);
end entity mux;

architecture mux_beh of mux is
begin
out_mux<=input(conv_integer(ctrl));
end architecture mux_beh;

component used in this design-------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge IS
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=24; -- total control signal width--mem
out
no_out,no_ctrl :integer :=6); -- no of output
signals(r),no.of control signals (V)

port( input:in std_logic_vector(input_w-1 downto 0);
tctrl: in std_logic_vector(tctrl_w-1 downto 0);
out_fmuxut std_logic_vector(no_out-1 downto 0));
END ENTITY mux_ge;

--
ARCHITECTURE mux_ge_str OF mux_ge IS

component mux

generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector(input_w-1 downto 0);
ctrl:in std_logic_vector(ictrl_w-1 downto 0);
out_mux: out std_logic);
end component mux;

--type z is array(0 to no_out-1) of std_logic;
--signal out_vec :std_logic_vector(no_out-1 downto 0);

BEGIN
ge1:for i in 0 to no_out-1 generate
--temp(i)<=tctrl((i*ictrl_w)+(ictrl_w-1) downto i*ictrl_w);
mut1:mux port map(input,tctrl((i*ictrl_w)+(ictrl_w-1) downto
i*ictrl_w),out_fmux(i));
end generate ge1;
--out_fmux<=out_vec;

END ARCHITECTURE mux_ge_str;

configuration mux_ge_config of mux_ge is
for mux_ge_str
for mut1:mux
use entity work.mux(mux_beh);
end for;
end for;
end configuration mux_ge_config;

 

[srinukasam]

hi Eyck
You have to add one more 'for ge1'/'end for' statement for the for loop
in the architecture...

i added the configuration statement for that ge1 for loop only , i think.
i didnt understood why i need one more like this.

for ge1
use entity work.mux(mux_beh);
end for;

even if i add also its giving the same error as
Error: ..component instance mux1:mux not found.(error point to first end
for)

 

[Eyck Jentzsch]

srinukasam wrote:

Hello
I designed one simple mux , then I instantiated the basic mux with
generate loop for more outputs.while compiling with model sim its giving
error as
Error: ..component instance mux1:mux not found.
Is the problem with configuration statement or any others..
Please help me
thank you

DESIGN:used as a component --------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux is
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector (input_w-1 downto 0);
ctrl: in std_logic_vector (ictrl_w-1 downto 0);
out_muxut std_logic);
end entity mux;

architecture mux_beh of mux is
begin
out_mux<=input(conv_integer(ctrl));
end architecture mux_beh;

component used in this design-------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge IS
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=24; -- total control signal width--mem
out
no_out,no_ctrl :integer :=6); -- no of output
signals(r),no.of control signals (V)

port( input:in std_logic_vector(input_w-1 downto 0);
tctrl: in std_logic_vector(tctrl_w-1 downto 0);
out_fmuxut std_logic_vector(no_out-1 downto 0));
END ENTITY mux_ge;

--
ARCHITECTURE mux_ge_str OF mux_ge IS

component mux

generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector(input_w-1 downto 0);
ctrl:in std_logic_vector(ictrl_w-1 downto 0);
out_mux: out std_logic);
end component mux;

--type z is array(0 to no_out-1) of std_logic;
--signal out_vec :std_logic_vector(no_out-1 downto 0);

BEGIN
ge1:for i in 0 to no_out-1 generate
--temp(i)<=tctrl((i*ictrl_w)+(ictrl_w-1) downto i*ictrl_w);
mut1:mux port map(input,tctrl((i*ictrl_w)+(ictrl_w-1) downto
i*ictrl_w),out_fmux(i));
end generate ge1;
--out_fmux<=out_vec;

END ARCHITECTURE mux_ge_str;

configuration mux_ge_config of mux_ge is
for mux_ge_str
for mut1:mux
use entity work.mux(mux_beh);
end for;
end for;
end configuration mux_ge_config;


You have to add one more 'for ge1'/'end for' statement for the for loop

in the architecture...

-Eyck

 

[Eyck Jentzsch]

srinukasam wrote:

hi Eyck
You have to add one more 'for ge1'/'end for' statement for the for loop
in the architecture...

i added the configuration statement for that ge1 for loop only , i think.
i didnt understood why i need one more like this.

for ge1
use entity work.mux(mux_beh);
end for;

even if i add also its giving the same error as
Error: ..component instance mux1:mux not found.(error point to first end
for)

The generate statement opens a new block inside the VHDL unit (the same

way like the 'block' statement does), therefore you have to *add* it to
the configration:
configuration mux_ge_config of mux_ge is
for mux_ge_str -- this is the 'block configuration' for the
-- architecture
for ge1: -- this is the 'block configuration' of the generate
-- statement
for mut1:mux -- this is the 'configuration specification'
-- of the component
use entity work.mux(mux_beh);
end for;
end for;
end for;
end configuration mux_ge_config;
An alternative way would be to use the 'all' instead of an instantiation
label:
for all:mux use entity work.mux(mux_beh); end for;

HTH

-Eyck