Configuration Altera Decives using EPC16 in PPS mode

T

tal_h

Guest
Hi,
I have a problem in configurating altera devices in my board.
my configuration scheme is as follows:
1 EPC16 device connected in PPS mode to:
A stratix device connected to Data0 (EP1S20) & 2 cyclone devices
(EP1C12) connected to Data1 & Data2 of the EPC16…
When I power-up the board => the Configuration isn't done.
I've looked on the nSTATUS & CONF_DONE signals and they look fine!
the CONF_DONE stays LOW all the time. the nSTATUS goes HIGH ~85mSec
after power is stable.
the DCLK signals stays LOW all the time! (there isn't DCLK)
I've tried an external OSC to the EPC16 => still the same phenomenon.
Please Advice!
Tal
 
tal_h@elbit.co.il (tal_h) wrote in message news:<7fc7c85.0402110004.797bdc7f@posting.google.com>...
Hi,
I have a problem in configurating altera devices in my board.
my configuration scheme is as follows:
1 EPC16 device connected in PPS mode to:
A stratix device connected to Data0 (EP1S20) & 2 cyclone devices
(EP1C12) connected to Data1 & Data2 of the EPC16…
When I power-up the board => the Configuration isn't done.
I've looked on the nSTATUS & CONF_DONE signals and they look fine!
the CONF_DONE stays LOW all the time. the nSTATUS goes HIGH ~85mSec
after power is stable.
the DCLK signals stays LOW all the time! (there isn't DCLK)
I've tried an external OSC to the EPC16 => still the same phenomenon.
Please Advice!
Tal
Click to expand...
Hi Tal,
The EPC16 should be driving out the DCLK signal, so figuring out why
this does not happen is key. However it's hard to say exactly what is
the problem based on this description. Here's a few things to try:

1. Make sure that the MSEL pins are set correctly on the FPGAs. PPS is
the acronym for Passive Parallel Synchronous - but the setup where one
EPC16 drives multiple FPGAs in parallel like this is called Concurrent
Configuration, and each FPGA should be set to Passive Serial as each
is receiving a serial stream.

2. Make sure the PGM pins are set correctly on the EPC16 to show which
page of data you want to access. If you are not doing anything special
like storing multiple configurations, they should be set to 0.

3. There are some external connections that must be made on the EPC16.
The F-RP# pin must be connected to the C-RP# pin. And the F-WE# pin
must be connected to the C-WE# pin. This connection is because the
EPC16 actually has two dice in it - a Flash and a controller. During
the production test, the Flash pins are driven to 12 V, but the
controller cannot handle this, therefore the connection cannot be made
in the package.

4. The FPGA VCCINT must be powered before the POR on the EPC16
expires. The POR can be set to 2 ms or 100 ms by using the PORSEL pin
- if you drive PORSEL low, then the POR is 100 ms. If this is not
done, then the EPC16 will never start configuration and you will not
see DCLK toggle.

Hopefully one of these solves the problem. If not, please check out
the FPGA Configuration Troubleshooter found on this web site:
http://www.altera.com/cgi-bin/ts.pl?fn=configuration

And if that doesn't work, then you may need to call the distributor,
FAE, or AE for some more assistance as the problem debug starts to get
very specific.

Sincerely,
Greg Steinke
Altera Corporation
gregs@altera.com
 
gregs@altera.com (Greg Steinke) wrote in message news:<5c1de958.0402121458.4c1cc566@posting.google.com>...
tal_h@elbit.co.il (tal_h) wrote in message news:<7fc7c85.0402110004.797bdc7f@posting.google.com>...
Hi,
I have a problem in configurating altera devices in my board.
my configuration scheme is as follows:
1 EPC16 device connected in PPS mode to:
A stratix device connected to Data0 (EP1S20) & 2 cyclone devices
(EP1C12) connected to Data1 & Data2 of the EPC16…
When I power-up the board => the Configuration isn't done.
I've looked on the nSTATUS & CONF_DONE signals and they look fine!
the CONF_DONE stays LOW all the time. the nSTATUS goes HIGH ~85mSec
after power is stable.
the DCLK signals stays LOW all the time! (there isn't DCLK)
I've tried an external OSC to the EPC16 => still the same phenomenon.
Please Advice!
Tal

Hi Tal,
The EPC16 should be driving out the DCLK signal, so figuring out why
this does not happen is key. However it's hard to say exactly what is
the problem based on this description. Here's a few things to try:

1. Make sure that the MSEL pins are set correctly on the FPGAs. PPS is
the acronym for Passive Parallel Synchronous - but the setup where one
EPC16 drives multiple FPGAs in parallel like this is called Concurrent
Configuration, and each FPGA should be set to Passive Serial as each
is receiving a serial stream.

2. Make sure the PGM pins are set correctly on the EPC16 to show which
page of data you want to access. If you are not doing anything special
like storing multiple configurations, they should be set to 0.

3. There are some external connections that must be made on the EPC16.
The F-RP# pin must be connected to the C-RP# pin. And the F-WE# pin
must be connected to the C-WE# pin. This connection is because the
EPC16 actually has two dice in it - a Flash and a controller. During
the production test, the Flash pins are driven to 12 V, but the
controller cannot handle this, therefore the connection cannot be made
in the package.

4. The FPGA VCCINT must be powered before the POR on the EPC16
expires. The POR can be set to 2 ms or 100 ms by using the PORSEL pin
- if you drive PORSEL low, then the POR is 100 ms. If this is not
done, then the EPC16 will never start configuration and you will not
see DCLK toggle.

Hopefully one of these solves the problem. If not, please check out
the FPGA Configuration Troubleshooter found on this web site:
http://www.altera.com/cgi-bin/ts.pl?fn=configuration

And if that doesn't work, then you may need to call the distributor,
FAE, or AE for some more assistance as the problem debug starts to get
very specific.

Sincerely,
Greg Steinke
Altera Corporation
gregs@altera.com
Click to expand...
Hi Greg,

Thank you for your reply.

Here are some more facts regarding to my board:

1. the VCCINT is stablized in about ~1mSec after power-up. the POR is
configured to 100mSec.

2. all of the MSEL & PGM pins are configured correctly.

3. the EPC16 Flash interface pins (address. data etca) are connected
to a HOST. first, I had problems in programing the EPC16 through
ByteBlaster, So I've disbled the HOST permentlay (all of its pins are
HIGH-Z always) & the programing worked!

4. I forgot to connect the nIO_PULL pin of the EP1S20 device to GND /
VCC, I can't connect it because it hasn't got a VIA on the PCB, So it
left un-connected.

5. I've tried power-sequencing:
a. I've powered the EPC16 VCC before the FPGA's VCCINT & VCCIO & the
configuration worked!
b. I've tried also the opposite sequence. first, I've powered the
FPGA's
VCCINT & VCCIO and then I've powered the EPC16 VCC and the
configuration
ALSO WORKED!!!!
c. when I don't have power-sequnce the configuration isn't
working!!!!!!

I've talked with my distributer & he hasn't got a clue....

please advice next...

Thanks,

Tal
 
I have communicated with Tal about this off-line. For those of you who
may see something similar -
The problem was that the EPC16 address and data lines were also
connected to a microprocessor. This microprocessor was supposed to
tristate the lines when a certain signal was active. Once the
connection between the EPC16 and the microprocessor was physically
cut, then the configuration worked. So something funny is going on
with the microprocessor.
The reason this is a problem is that the EPC16 has the flash die and
the controller die in one package. During configuration, the
controller is exercising the flash. This activity is on the flash
address and data pins, which are connected to external pins. So if an
external device is doing something to those pins then configuration
can fail.
To help future customers we will add this scenario to our
Configuration Troubleshooter tool on the Altera web site.

Regards,
Greg Steinke
gregs@altera.com
Altera Corporation
 
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