Conecting a memory to a cache

[Rafael Almeida]

I think I probably won't get answer, as I need this for tomorrow, but this is kind
of my last shot, I've tried everything already and nothing seems to work. My
verilog knowledge is fairly limited, but I wanted to do a cache to be used by a z80
processor. The thing is that I send an address to the memory and it doesn't seem to
answer it back until i try to get a new address to which it answers wtih the old
value from the last address I passed.
The memory is 32 m6116, where each m6116 is implemented as:
module m6116 (A, D, WE_N, CE_N, OE_N);
input[10:0] A;
input WE_N, CE_N, OE_N;

inout[7:0] D;

wire[7:0] D_IN;

reg[7:0] D_OUT;
reg[7:0] MEM[0:2047];

assign D[7:0] = (~CE_N && ~OE_N) ? D_OUT[7:0] : 8'bz;
assign D_IN[7:0] = D[7:0];

always @(CE_N or WE_N or OE_N or A or D)
begin
if (~CE_N) begin
if (~WE_N)
MEM[A[10:0]] = D_IN[7:0];
else
D_OUT[7:0] = MEM[A[10:0]];
end
end

initial
begin
$readmemh("teste", MEM);
end
endmodule
They are putted together with
module memory (A, D, WE_N, CE_N, OE_N);
input[15:0] A;
input WE_N;
input CE_N;
input OE_N;
inout[7:0] D;


m6116 m0 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd0), OE_N);
m6116 m1 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd1), OE_N);
m6116 m2 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd2), OE_N);
m6116 m3 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd3), OE_N);
m6116 m4 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd4), OE_N);
m6116 m5 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd5), OE_N);
m6116 m6 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd6), OE_N);
m6116 m7 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd7), OE_N);
.
.
.
endmodule

So connecting this memory with the z80 directly seems to work fine, but if i place
a m6116 in the middle the situation i described earlier occurs. I've tried to sync
the cache with the clock and it didn't work either. I even tried making the memory
fetch take two cycles on the cache (using the WAIT processor pin), but no luck
either. If someone can give me a suggestion on how to do it i'd be really pleased!

 

[John_H]

Look at the sensitivity list you ahve for your memory read/write arrays:
always @(CE_N or WE_N or OE_N or A or D)

WHAT are you trying to do with this? To have a realizable memory, the write
has to be synchronous or have an appropriately sized write strobe. The read
in modern FPGAs would typically be synchronous as well since asynchronous
memories (change the address and the data changes without a clock) are much
slower than the synchronous types.

For an asynchronous memory:
always @(negedge WE_N) // assuming you want WE going active, not going
inactive
if( ~CE_N ) MEM[A[10:0]] <= D_IN[7:0];
assign D_OUT[7:0] = MEM[A[10:0]];

You need a clock for a real synchronous design.


always @(posedge clk)
begin
if( ~CE_N & ~WE_N) MEM[A[10:0]] <= D_IN[7:0];
D_OUT[7:0] <= MEM[A[10:0]];
end

The data will be present after the clock edge where the address and chip
enable occur.


"Rafael Almeida" <rafaelc@dcc.ufmg.br> wrote in message
news:dnsclc$af2$1@domitilla.aioe.org...

I think I probably won't get answer, as I need this for tomorrow, but this
is kind of my last shot, I've tried everything already and nothing seems to
work. My verilog knowledge is fairly limited, but I wanted to do a cache to
be used by a z80 processor. The thing is that I send an address to the
memory and it doesn't seem to answer it back until i try to get a new
address to which it answers wtih the old value from the last address I
passed.
The memory is 32 m6116, where each m6116 is implemented as:
module m6116 (A, D, WE_N, CE_N, OE_N);
input[10:0] A;
input WE_N, CE_N, OE_N;

inout[7:0] D;

wire[7:0] D_IN;

reg[7:0] D_OUT;
reg[7:0] MEM[0:2047];

assign D[7:0] = (~CE_N && ~OE_N) ? D_OUT[7:0] : 8'bz;
assign D_IN[7:0] = D[7:0];

always @(CE_N or WE_N or OE_N or A or D)
begin
if (~CE_N) begin
if (~WE_N)
MEM[A[10:0]] = D_IN[7:0];
else
D_OUT[7:0] = MEM[A[10:0]];
end
end

initial
begin
$readmemh("teste", MEM);
end
endmodule
They are putted together with
module memory (A, D, WE_N, CE_N, OE_N);
input[15:0] A;
input WE_N;
input CE_N;
input OE_N;
inout[7:0] D;


m6116 m0 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd0), OE_N);
m6116 m1 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd1), OE_N);
m6116 m2 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd2), OE_N);
m6116 m3 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd3), OE_N);
m6116 m4 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd4), OE_N);
m6116 m5 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd5), OE_N);
m6116 m6 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd6), OE_N);
m6116 m7 (A[10:0], D, WE_N, !({CE_N, A[15:11]} == 6'd7), OE_N);
.
.
.
endmodule

So connecting this memory with the z80 directly seems to work fine, but if
i place a m6116 in the middle the situation i described earlier occurs.
I've tried to sync the cache with the clock and it didn't work either. I
even tried making the memory fetch take two cycles on the cache (using the
WAIT processor pin), but no luck either. If someone can give me a
suggestion on how to do it i'd be really pleased!