Conditional "FOR..GENERATE" generic construct?

[Pasacco]

Hi

I have problem with using "FOR...GENERATE" of generic component.

My goal is to use "FOR...GENERATE" construct,
in order to instantiate different modules,
depending on condition.

"Exercise1" below works fine.

"Exercise2"-style of construct below does not work.

Question is that
Does VHDL support "Exercise2" style of construct?

If yes, could anyone point out where I can find some examples?

----------------------------------------------------------------
-- Exercise1 : Homogeneous modules
---------------------------------------------------------------
-- MAX : maximum number of instantiated components

CTRL : for i in 0 to MAX-1 generate
Module : Logic_Module
port map(
CLK => CLK, -- clock
RST => RST, -- reset
IN1_i => IN1(i), -- input port
OUT1_o => OUT1(i) ); -- output port
end generate CTRL;
---------------------------------------------------------------

----------------------------------------------------------------
-- Exercise2: Trying to optimize heterogenous modules
-- Temp : integer type signal
---------------------------------------------------------------
CTRL : for i in 0 to MAX-1 generate

if Temp(i) = 0 then --- In this condition, instantiate Logic_ModuleA

ModuleA : Logic_ModuleA
port map(
CLK => CLK,
RST => RST,
IN1_i => IN1(i),
OUT1_o => OUT1(i) );

else --- In this condition, instantiate Logic_ModuleB

ModuleB : Logic_ModuleB
port map(
CLK => CLK,
RST => RST,
IN1_i => IN1(i),
OUT1_o => OUT1(i) );

end generate CTRL;
---------------------------------------------------------------

 

[Jonathan Bromley]

On 18 May 2007 08:31:36 -0700,
Pasacco <pasacco@gmail.com> wrote:

----------------------------------------------------------------
-- Exercise2: Trying to optimize heterogenous modules
-- Temp : integer type signal
---------------------------------------------------------------
CTRL : for i in 0 to MAX-1 generate

if Temp(i) = 0 then --- In this condition, instantiate Logic_ModuleA

You need another nested GENERATE construct for this "if".

MOD_CHOICE_A: if Temp(i) = 0 generate

ModuleA : Logic_ModuleA
port map(
CLK => CLK,
RST => RST,
IN1_i => IN1(i),
OUT1_o => OUT1(i) );
end generate; -- MOD_CHOICE

else --- In this condition, instantiate Logic_ModuleB

Sadly, you cannot have ELSE on IF...GENERATE, so you must do...

MOD_CHOICE_B: if Temp(i) /= 0 generate

ModuleB : Logic_ModuleB
....

Note, also, that Temp() must be a constant of some kind -
a generic, or a constant. No signals, no variables.

Hope this helps
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Colin Paul Gloster]

In news:1qhr439auktl0n9smeetck0vr4gp5mauls@4ax.com timestamped Fri, 18
May 2007 16:37:35 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> posted:
"[..]

Sadly, you cannot have ELSE on IF...GENERATE, [..]

[..]"

ELSE is allowed for GENERATE in Draft IEEE P1076/D3.4, April 26, 2007
but I am not aware of a tool which supports this.

 

[Pasacco]

Synthesizer synthesizes as expected.
While functionality is under test,
Your remark was very helpful.
Thank you.