concats of parameters, legal verilog or no?

[Chris F Clark]

I had a piece of verilog pass by my desk the other day that our
"standard" simulator cannot handle (our home-brew one does, but that's
not relevant). The important question is the code valid verilog or
can it be massaged into valid verilog. If it's valid verilog at least
we know that the problem lies in the simulator and not in the code.
If it's not valid verilog, then we have to fix it.

module mod(out);

parameter param = 32'b0;

output [31:0] out;
wire [31:0] out = {1{param}}; // the concat is the problem

endmodule

The question is do parameters have self-defined widths, as required by
expressions used inside a concat? If not, is there a standard
conforming way (i.e. portable) to give a parameter a width?

Thanks for any suggestions,
-Chris

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Compiler Resources, Inc. Web Site : http://world.std.com/~compres
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[Stephen Williams]

Chris F Clark wrote:

module mod(out);

parameter param = 32'b0;

output [31:0] out;
wire [31:0] out = {1{param}}; // the concat is the problem

endmodule

The question is do parameters have self-defined widths, as required by
expressions used inside a concat? If not, is there a standard
conforming way (i.e. portable) to give a parameter a width?

The way to be sure is to rewrite it as:

parameter [31:0] param = 0;

This way the user of you module can override the value, without
overriding the size of the parameter. The way you have it written,
the parameter takes on the size of the expression, which may not
be defined if for example "defparam mod.param = 0" is found in
your code.

(NOTE: Icarus Verilog handles the legal cases, but doesn't complain
about the illegal example I gave. Oops!)
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[David Jones]

In article <sddekt9bg6s.fsf_-_@shell01.TheWorld.com>,
Chris F Clark <cfc@shell01.TheWorld.com> wrote:

module mod(out);

parameter param = 32'b0;

output [31:0] out;
wire [31:0] out = {1{param}}; // the concat is the problem

endmodule

The question is do parameters have self-defined widths, as required by
expressions used inside a concat? If not, is there a standard
conforming way (i.e. portable) to give a parameter a width?

It should also be noted that commercial tools are often lax about
enforcing the "must have width inside concatenation" rule.

The OpenRISC or1200 code has this problem, but it apparently simulates
and synthesizes just fine. My homebrew tool rejects it though.

 

[Stephen Williams]

David Jones wrote:

In article <sddekt9bg6s.fsf_-_@shell01.TheWorld.com>,
Chris F Clark <cfc@shell01.TheWorld.com> wrote:

The question is do parameters have self-defined widths, as required by
expressions used inside a concat? If not, is there a standard
conforming way (i.e. portable) to give a parameter a width?


It should also be noted that commercial tools are often lax about
enforcing the "must have width inside concatenation" rule.

The OpenRISC or1200 code has this problem, but it apparently simulates
and synthesizes just fine. My homebrew tool rejects it though.

In fact, some *very* *expensive* commercial tools are very
lax about this rule. I (Icarus Verilog) have gotten plenty
of reports from people with very hidden bugs in their Verilog
saying that "GAET-X(1) compiles this fine." If it's a FAQ on
the Icarus Verilog web site, it is explained in great detail
in the "ieee-notes.txt" file that comes with Icarus Verilog
distributions.


(1) God-Awful Expensive Tool
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."