Concatenation operator, value ordering, bug in ModelSim, or

[Edmond Coté]

Hi,

I've been experiencing a weird problem with ModelSim and
SystemVerilog. I've been trying to do the following:

assign fifo.data_in = { bus.address, bus.command, bus.request_tag };
assign { fifo_address, fifo_command, response_tag } = fifo.data_out;

However, on one system, I need to interchange the 2nd line with the
following (note the reversed values):

assign { response_tag, fifo_command, fifo_address } = fifo.data_out;

Is what I'm doing legal? Why is there a discrepancy between two
systems, and more importantly, what will my synthesis tool make of
this!

Thanks,

Edmond

 

[Ajeetha (www.noveldv.com)]

Hi,
You didn't mention what the two "systems" you talked about - Linux
and Solaris? Is it 32-bit or 64-bit?

On Feb 13, 8:04 pm, "Edmond Coté" <edmond.c...@gmail.com> wrote:

Hi,

I've been experiencing a weird problem with ModelSim and
SystemVerilog. I've been trying to do the following:

assign fifo.data_in = { bus.address, bus.command, bus.request_tag };
assign { fifo_address, fifo_command, response_tag } = fifo.data_out;

Are the data widths matching in LHS & RHS?

However, on one system, I need to interchange the 2nd line with the
following (note the reversed values):

assign { response_tag, fifo_command, fifo_address } = fifo.data_out;

Is what I'm doing legal?

I would imagine both to be legal.

Why is there a discrepancy between two
systems, and more importantly, what will my synthesis tool make of
this!

Need more data (on the widths of each signal involved) to say for
sure. It may also be a bug in the tool.

Ideally speaking your tool should flag width mismatches, I know VCS
does it most of the time. If not try a good design checker such as
Spyglass/Leda etc.

HTH
Ajeetha, CVC
www.noveldv.com

Thanks,

Edmond