Concatenate String in Verilog?

[Davy]

Hi all,
I want to open a lot of files and read data to reg.

something like
//-----code--------
$readmemh(".\pattern\0.dat",inmem0);
$readmemh(".\pattern\1.dat",inmem1);
....
$readmemh(".\pattern\49.dat",inmem49);
//-----code end----

I want to use something like strcat() in C to concatenate the string.
So, I can use a loop to replace large block of code above.
Is there any method to do this work in Verilog?

Any suggestions will be appreciated!
Best regards,
Davy

 

[Jamie]

Davy wrote:

Hi all,
I want to open a lot of files and read data to reg.

something like
//-----code--------
$readmemh(".\pattern\0.dat",inmem0);
$readmemh(".\pattern\1.dat",inmem1);
...
$readmemh(".\pattern\49.dat",inmem49);
//-----code end----

I want to use something like strcat() in C to concatenate the string.
So, I can use a loop to replace large block of code above.
Is there any method to do this work in Verilog?

Any suggestions will be appreciated!
Best regards,
Davy

the registry is not your play ground.
it is not your database of life long collections.

simply put, its use should be limited to storing
data that is truly needed via other apps or tools
of yours to access information that other wise would
be hard to find..!
what this means is, you put things like file paths
to where you mite be storing large segments of data.

please don't do us any favors by passing around
bad idea's for other nobs to follow.



--
Real Programmers Do things like this.
http://webpages.charter.net/jamie_5

 

[motty]

Sorry Davy, but I don't know the answer to your problem, and I may be
criticized for posting but....

What are you talking about Jamie? Windows registry? Did you happen to
read the question? Or did you happen to notice the forum you were in?
Dave is posing a Verilog question and the reg he is referring to is not
the Windows registry what so ever!!

So please don't do US any favors by replying with something totally off
base! And it's noob, not nob. And it's might, not mite. Mites are
bugs. Not software bugs!

Good luck with your query Davy!! There is probably some SystemVerilog
or PLI stuff that would do the trick...

 

To concatenate strings in Verilog, you can generally just use vector
concatenation of the regs containing the string values. However, you
should remain aware that it is not really a string concatenation,
because that matters in some situations. For example, if you tried to
do

reg [8*80:1] dir_name, file_name, full_name;

initial
begin
dir_name = "./mydir/";
file_name = "file.dat";
full_name = {dir_name, file_name};
$display("%s", full_name);
end

This won't work, because file_name is not just "file.dat". It is
"file.dat" with an extra 70 null or zero bytes in front of it. Those
extra nulls will appear in the concatenation too. That 160 byte wide
concatenation will get truncated back to 80 bytes when assigned to
full_name, losing the part from dir_name entirely. But if you declared
file_name to be 10 bytes, dir_name to be 70 bytes, and full_name to be
80 bytes, then everything would fit without any truncation.

Note that this also relies on the tools to ignore the embedded null
characters in the full name when it is passed to a system task like
$readmem, which some might not do.

Another way to build filenames with Verilog-2001 would be to use
$swrite to print the filename, including numbers from loop counters,
into a reg variable.