composite inout signals with different driver directions

[Ralph Friedrich]

Hello,
I'm use vectors to combine signals with different driver directions.
May be that's not a good coding style ?!


T(
Q : INOUT Std_logic_vector (24 DOWNTO 0) ;
....

For example:
Q(12 downto 0) is driven by the testbech.
Q(24 downto 13) is driven by DUT.

In the simulation I get there a X on some signals.

When I set a init value to the vector it works sometimes.

Does anyone know whats going on?

 

[Jim Lewis]

Ralph,
Initially the testbench and the DUT are driving
driving all elements of the array. If one does
not drive a field, the value it is effectively
driving is 'U', the left most value of std_ulogic.

A simple way to get around this is to initialize
the port to all 'Z' as follows:

T(
Q : INOUT Std_logic_vector (24 DOWNTO 0) := (others => 'Z') ;
...

Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Ralph Friedrich wrote:

Hello,
I'm use vectors to combine signals with different driver directions.
May be that's not a good coding style ?!


T(
Q : INOUT Std_logic_vector (24 DOWNTO 0) ;
...

For example:
Q(12 downto 0) is driven by the testbech.
Q(24 downto 13) is driven by DUT.

In the simulation I get there a X on some signals.

When I set a init value to the vector it works sometimes.

Does anyone know whats going on?