Components instantiation in loop?

[VHDL User]

Hi All,
Suppose I have adder blocks (2 input) written out in VHDL.Using these I
want to generate a function : Sigma(i=1 to b){X(i)}.
where X(i) are elements of a b-bit array.
SO,essentially,I have to sum the elements of a b-bit array using these 2
input adders;b is a generic.
I suppose I will need b-1 adders of 2 inputs.
How do I instantiate these adders in a loop?

entity summer is
generic (b:Integer ) --Do I have to initialise this??
port (X:in array(0 to b-1) of integer; --Is this allowed? or do I use
Yut integer); --unbounded array
end summer;

arcitecture behave of summer is
begin
process(X)
begin
for i in 0 to X´length-1
..--I need to create b-1 adders .How do I go about it? Where do I put
component statement?

Thanks a lot everyone.

 

[Egbert Molenkamp]

The straightforward solution of your problem would be a process with a for
loop that add X(i) to the sum(i-1).
However since you like to use an entity, when I'm correct, you can not
include this as a component in a sequential statement (process).
However you can use a generate statement.
A complete solution is give below.

If you look to the structure then you will probably get a long chain of
adders. I don't think that the synthesis tool will rearrange the adders so
that you get a tree like structure to improve speed. The behavioural
description (loop and adding X(i) to the previous sum) will probably get a
better result.
However you can also write the tree like structure using generate
statements; not added.

Egbert Molenkamp

package types is
type integer_array is array (natural range <&gt of integer;
end types;

entity add2 is
port (x,y : in integer; sum : out integer);
end add2;

architecture behaviour of add2 is
begin
sum <= x + y;
end;

use work.types.all;
entity summer is
generic (b:Integer:=5 ); --Do I have to initialise this?? no
port (X :in integer_array(0 to b-1);
Y ut integer);
end summer;

architecture behave of summer is
signal int : integer_array(0 to b);
constant first : integer := 0;
begin
int(0) <= first;

ripple:for i in 0 to b-1 generate
adder:entity work.add2 port map(int(i),X(i),int(i+1));
end generate;

Y <= int(b);

end behave;


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Hi All,
Suppose I have adder blocks (2 input) written out in VHDL.Using these I
want to generate a function : Sigma(i=1 to b){X(i)}.
where X(i) are elements of a b-bit array.
SO,essentially,I have to sum the elements of a b-bit array using these 2
input adders;b is a generic.
I suppose I will need b-1 adders of 2 inputs.
How do I instantiate these adders in a loop?

entity summer is
generic (b:Integer ) --Do I have to initialise this??
port (X:in array(0 to b-1) of integer; --Is this allowed? or do I use
Yut integer); --unbounded array
end summer;

arcitecture behave of summer is
begin
process(X)
begin
for i in 0 to X´length-1
..--I need to create b-1 adders .How do I go about it? Where do I put
component statement?

Thanks a lot everyone.