Components instantiation in loop?

[VHDL User]

Hi All,
Suppose I have adder blocks (2 input) written out in VHDL.Using these I
want to generate a function : Sigma(i=1 to b){X(i)}.
where X(i) are elements of a b-bit array.
SO,essentially,I have to sum the elements of a b-bit array using these 2
input adders;b is a generic.
I suppose I will need b-1 adders of 2 inputs.
How do I instantiate these adders in a loop?

entity summer is
generic (b:Integer ) --Do I have to initialise this??
port (X:in array(0 to b-1) of integer; --Is this allowed? or do I use
Yut integer); --unbounded array
end summer;

arcitecture behave of summer is
begin
process(X)
begin
for i in 0 to X´length-1
..--I need to create b-1 adders .How do I go about it? Where do I put
component statement?

Thanks a lot everyone.