component usage

M

mkr

Guest
I am new to vhdl and trying to understand the following code for
parity generator. This is compiling in modelsim without any issues but
I don't seem to understand where the logic for xor2 is? I see xor2
declared as component with only interface but I don't find the
implementation. Can anyone help me understand this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity parity is
port(
datain : in unsigned(3 downto 0);
pout : out std_logic);
end entity;

architecture synth of parity is

signal a,b,x : std_logic ;

component xor2 port (x, y: IN std_logic; z: OUT std_logic);
end component;

begin
x1: xor2 port map ( datain(0), datain(1), a ) ;
x2: xor2 port map ( datain(2), datain(3), b ) ;
x3: xor2 port map ( a,b,x);
end synth;

Thanks
 
mkr wrote:

I am new to vhdl and trying to understand the following code for
parity generator. This is compiling in modelsim without any issues but
I don't seem to understand where the logic for xor2 is? I see xor2
declared as component with only interface but I don't find the
implementation. Can anyone help me understand this?
Click to expand...
You still need an entity/architecture pair supplying the functionality of
xor2. Compile it just as you have compiled the code of entity/architecture
parity/synth.

In VHDL, declaring a component is enough to be able to instantiate it. The
matching entity need not be compiled first.

When loading a design, if a matching entity is found it is loaded as well.
This is called "binding". If it is not found, the component is left
unbound: it leaves a hole in your design. Depending on the simulator
settings, the error is fatal or non-fatal error. The default for ModelSim
is non-fatal.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
On May 21, 1:50 pm, mkr <mahenre...@gmail.com> wrote:
I am new to vhdl and trying to understand the following code for
parity generator. This is compiling in modelsim without any issues but
I don't seem to understand where the logic for xor2 is? I see xor2
declared as component with only interface but I don't find the
implementation. Can anyone help me understand this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity parity is
port(
datain : in unsigned(3 downto 0);
pout : out std_logic);
end entity;

architecture synth of parity is

signal a,b,x : std_logic ;

component xor2 port (x, y: IN std_logic; z: OUT std_logic);
end component;

begin
x1: xor2 port map ( datain(0), datain(1), a ) ;
x2: xor2 port map ( datain(2), datain(3), b ) ;
x3: xor2 port map ( a,b,x);
end synth;

Thanks
Click to expand...
Paul addressed the issue with components, but you should also know
that as of vhdl-93, components are no longer required intermediaries
for entity/architecture instantiation. You can directly instantiate
the entity/architecture without declaring or using a like component.

For an example:

x1: entity work.xor2(rtl) port map ( datain(0), datain(1), a);

The example assumes that the entity "xor2" and its architecture "rtl"
are both already compiled in the same library into which this entity/
architecture (parity/synth) is being compiled. Replace "work" with the
name of the library that does contain them if work does not. You can
also leave off the "(rtl)" to automatically bind to the most recently
analyzed architecture for xor2. I'm not sure what kind of notification
you'll get if no compiled architecture for xor2 exists.

Andy
 
Thank you. got it now.

Also, what is the need for vendor specific libraries for functional
simulation? I see lot of device specific libraries in ModelSim Altera
edition for different Altera FPGAs and some of them contain even
primitive gates. Why do we need to use vendor/device specific
libraries over standard vhdl libraries for functional simulation?


On May 22, 2:35 am, Andy <jonesa...@comcast.net> wrote:
On May 21, 1:50 pm, mkr <mahenre...@gmail.com> wrote:





I am new to vhdl and trying to understand the following code for
parity generator. This is compiling in modelsim without any issues but
I don't seem to understand where the logic for xor2 is? I see xor2
declared as component with only interface but I don't find the
implementation. Can anyone help me understand this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity parity is
port(
datain : in unsigned(3 downto 0);
pout : out std_logic);
end entity;

architecture synth of parity is

signal a,b,x : std_logic ;

component xor2 port (x, y: IN std_logic; z: OUT std_logic);
end component;

begin
x1: xor2 port map ( datain(0), datain(1), a ) ;
x2: xor2 port map ( datain(2), datain(3), b ) ;
x3: xor2 port map ( a,b,x);
end synth;

Thanks

Paul addressed the issue with components, but you should also know
that as of vhdl-93, components are no longer required intermediaries
for entity/architecture instantiation. You can directly instantiate
the entity/architecture without declaring or using a like component.

For an example:

x1: entity work.xor2(rtl) port map ( datain(0), datain(1), a);

The example assumes that the entity "xor2" and its architecture "rtl"
are both already compiled in the same library into which this entity/
architecture (parity/synth) is being compiled. Replace "work" with the
name of the library that does contain them if work does not. You can
also leave off the "(rtl)" to automatically bind to the most recently
analyzed architecture for xor2. I'm not sure what kind of notification
you'll get if no compiled architecture for xor2 exists.

Andy- Hide quoted text -

- Show quoted text -
Click to expand...
 
Thank you. got it now.

Also, what is the need for vendor specific libraries for functional
simulation? I see lot of device specific libraries in ModelSim Altera
edition for different Altera FPGAs and some of them contain even
primitive gates. Why do we need to use vendor/device specific
libraries over standard vhdl libraries for functional simulation?


On May 22, 2:35 am, Andy <jonesa...@comcast.net> wrote:
On May 21, 1:50 pm, mkr <mahenre...@gmail.com> wrote:





I am new to vhdl and trying to understand the following code for
parity generator. This is compiling in modelsim without any issues but
I don't seem to understand where the logic for xor2 is? I see xor2
declared as component with only interface but I don't find the
implementation. Can anyone help me understand this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity parity is
port(
datain : in unsigned(3 downto 0);
pout : out std_logic);
end entity;

architecture synth of parity is

signal a,b,x : std_logic ;

component xor2 port (x, y: IN std_logic; z: OUT std_logic);
end component;

begin
x1: xor2 port map ( datain(0), datain(1), a ) ;
x2: xor2 port map ( datain(2), datain(3), b ) ;
x3: xor2 port map ( a,b,x);
end synth;

Thanks

Paul addressed the issue with components, but you should also know
that as of vhdl-93, components are no longer required intermediaries
for entity/architecture instantiation. You can directly instantiate
the entity/architecture without declaring or using a like component.

For an example:

x1: entity work.xor2(rtl) port map ( datain(0), datain(1), a);

The example assumes that the entity "xor2" and its architecture "rtl"
are both already compiled in the same library into which this entity/
architecture (parity/synth) is being compiled. Replace "work" with the
name of the library that does contain them if work does not. You can
also leave off the "(rtl)" to automatically bind to the most recently
analyzed architecture for xor2. I'm not sure what kind of notification
you'll get if no compiled architecture for xor2 exists.

Andy- Hide quoted text -

- Show quoted text -
Click to expand...
 
On May 22, 5:53 am, mkr <mahenre...@gmail.com> wrote:
Thank you. got it now.

Also, what is the need for vendor specific libraries for functional
simulation? I see lot of device specific libraries in ModelSim Altera
edition for different Altera FPGAs and some of them contain even
primitive gates. Why do we need to use vendor/device specific
libraries over standard vhdl libraries for functional simulation?

On May 22, 2:35 am, Andy <jonesa...@comcast.net> wrote:

On May 21, 1:50 pm, mkr <mahenre...@gmail.com> wrote:

I am new to vhdl and trying to understand the following code for
parity generator. This is compiling in modelsim without any issues but
I don't seem to understand where the logic for xor2 is? I see xor2
declared as component with only interface but I don't find the
implementation. Can anyone help me understand this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity parity is
port(
datain : in unsigned(3 downto 0);
pout : out std_logic);
end entity;

architecture synth of parity is

signal a,b,x : std_logic ;

component xor2 port (x, y: IN std_logic; z: OUT std_logic);
end component;

begin
x1: xor2 port map ( datain(0), datain(1), a ) ;
x2: xor2 port map ( datain(2), datain(3), b ) ;
x3: xor2 port map ( a,b,x);
end synth;

Thanks

Paul addressed the issue with components, but you should also know
that as of vhdl-93, components are no longer required intermediaries
for entity/architecture instantiation. You can directly instantiate
the entity/architecture without declaring or using a like component.

For an example:

x1: entity work.xor2(rtl) port map ( datain(0), datain(1), a);

The example assumes that the entity "xor2" and its architecture "rtl"
are both already compiled in the same library into which this entity/
architecture (parity/synth) is being compiled. Replace "work" with the
name of the library that does contain them if work does not. You can
also leave off the "(rtl)" to automatically bind to the most recently
analyzed architecture for xor2. I'm not sure what kind of notification
you'll get if no compiled architecture for xor2 exists.

Andy- Hide quoted text -

- Show quoted text -
Click to expand...
There are two reasons vendor specific libraries are used. One is that
they allow you to simulate the netlist resulting from synthesis (the
netlist includes vendor specific primitives that are modeled in the
library). Second is that for some cases, you may want to instantiate
vendor specific primitives, especially when your synthesis tool cannot
adequately infer them from your description.

Note that when you instantiate a primitive in synthesizable code, you
must use a component (the vendor library usually has a package of
component declarations for all the primitives, so you do not have to
declare the component yourself). That way, the synthesis tool sees an
unbound component that corresponds with a known vendor primitive, and
uses the primitive. During simulation, the simulator binds the
component instance to the vhdl entity/architecture in the vendor
library. So the same source code still works for synthesis and
simulation.

Andy
 
mkr wrote:

Also, what is the need for vendor specific libraries for functional
simulation?
Click to expand...
You don't if you write your own code.
See the vhdl synthesis guide.

I see lot of device specific libraries in ModelSim Altera
edition for different Altera FPGAs and some of them contain even
primitive gates. Why do we need to use vendor/device specific
libraries over standard vhdl libraries for functional simulation?
Click to expand...
Yes, they are a pain to use, but they are
not needed in most cases.
Basic counters, shifters, muxes,
block ram/rom etc. can be inferred from code
so that the synthesis and simulation model
are the same source file.

-- Mike Treseler
 
On May 22, 5:11 am, mkr <mahenre...@gmail.com> wrote:
Thank you. got it now.

Also, what is the need for vendor specific libraries for functional
simulation? I see lot of device specific libraries in ModelSim Altera
edition for different Altera FPGAs and some of them contain even
primitive gates. Why do we need to use vendor/device specific
libraries over standard vhdl libraries for functional simulation?

On May 22, 2:35 am, Andy <jonesa...@comcast.net> wrote:

On May 21, 1:50 pm, mkr <mahenre...@gmail.com> wrote:

I am new to vhdl and trying to understand the following code for
parity generator. This is compiling in modelsim without any issues but
I don't seem to understand where the logic for xor2 is? I see xor2
declared as component with only interface but I don't find the
implementation. Can anyone help me understand this?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity parity is
port(
datain : in unsigned(3 downto 0);
pout : out std_logic);
end entity;

architecture synth of parity is

signal a,b,x : std_logic ;

component xor2 port (x, y: IN std_logic; z: OUT std_logic);
end component;

begin
x1: xor2 port map ( datain(0), datain(1), a ) ;
x2: xor2 port map ( datain(2), datain(3), b ) ;
x3: xor2 port map ( a,b,x);
end synth;

Thanks

Paul addressed the issue with components, but you should also know
that as of vhdl-93, components are no longer required intermediaries
for entity/architecture instantiation. You can directly instantiate
the entity/architecture without declaring or using a like component.

For an example:

x1: entity work.xor2(rtl) port map ( datain(0), datain(1), a);

The example assumes that the entity "xor2" and its architecture "rtl"
are both already compiled in the same library into which this entity/
architecture (parity/synth) is being compiled. Replace "work" with the
name of the library that does contain them if work does not. You can
also leave off the "(rtl)" to automatically bind to the most recently
analyzed architecture for xor2. I'm not sure what kind of notification
you'll get if no compiled architecture for xor2 exists.

Andy- Hide quoted text -

- Show quoted text -
Click to expand...
Examples of primitives that you might need to instantiate include
clock manager (dll/pll) blocks, fifo memories (that use built in fifo
control logic), memories with different input/output data port widths
(again using built in hardware to accomplish), etc.

If you have to instantiate it, then you need a model of it to simulate
with the rest of your synthesis code. That's what the vendor libraries
are for.

Andy
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top