component statements within architecture statements

N

Neil Zanella

Guest
Hello,

I would like to ask a question concerning the intended use of component
statements within architecture statements in VHDL. Since when
instantiating different components the component part is optional, why
would anyone want to include it. Even if two entities were defined with an
interface with clashing signal names, the scope of those names would not
interfere when those entities are used for instantiation. So why would
anyone want to use an explicit component statement inside an architecture?

Thanks,

Neil
 
Neil Zanella wrote:

I would like to ask a question concerning the intended use of component
statements within architecture statements in VHDL. Since when
instantiating different components the component part is optional, why
would anyone want to include it. Even if two entities were defined with an
interface with clashing signal names, the scope of those names would not
interfere when those entities are used for instantiation. So why would
anyone want to use an explicit component statement inside an architecture?
Click to expand...
A component is a socket into which you can plug
any entity/architecture that fits using a configuration.

If there will only be one such module to plug in,
as is often the case, then direct instances
without component declarations make sense.

However, if you expect to plug in a different module in
the future, an indirect instance now may simplify
the future change while providing backward compatibility
with the first design.

-- Mike Treseler
 
So what is the correct syntax for instantiating an entity that is not in
your "work" library? I've never been able to figure out direct
instantiation of Xilinx unisim primitives - either ModelSim or Synplify (or
both) choke on everything I've tried. It seems like this should work...

library unisim;
use unisim.vcomponents.all;

....

Mult1 : entity unisim.MULT18X18
port map (P => P2, A => a(k,2), B => w0slv);

Thanks,
Barry Brown


"Mike Treseler" <tres@tc.fluke.com> wrote in message
news:3F8F8718.5020103@tc.fluke.com...
Neil Zanella wrote:

I would like to ask a question concerning the intended use of component
statements within architecture statements in VHDL. Since when
instantiating different components the component part is optional, why
would anyone want to include it. Even if two entities were defined with
an
interface with clashing signal names, the scope of those names would not
interfere when those entities are used for instantiation. So why would
anyone want to use an explicit component statement inside an
architecture?

A component is a socket into which you can plug
any entity/architecture that fits using a configuration.

If there will only be one such module to plug in,
as is often the case, then direct instances
without component declarations make sense.

However, if you expect to plug in a different module in
the future, an indirect instance now may simplify
the future change while providing backward compatibility
with the first design.

-- Mike Treseler
Click to expand...
 
I do it like this (example: a simple wrapper for the Xilinx ROC
primitive). XST seems smart enough to secan the named libraries (in
addition to work) to find ROC.

LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY XROC IS
PORT(
O : OUT std_ulogic
);
END XROC ;

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.VCOMPONENTS.all; -- Xilinx primitives

architecture xilinx of XROC is

begin
croc : component ROC -- Reset on Configuration
port map (
O => O);

end xilinx;

"Barry Brown" <barry_brown@agilent.com> wrote:

:So what is the correct syntax for instantiating an entity that is not in
:your "work" library? I've never been able to figure out direct
:instantiation of Xilinx unisim primitives - either ModelSim or Synplify (or
:both) choke on everything I've tried. It seems like this should work...
:
:library unisim;
:use unisim.vcomponents.all;
:
:...
:
: Mult1 : entity unisim.MULT18X18
: port map (P => P2, A => a(k,2), B => w0slv);
:
:Thanks,
:Barry Brown
:
:
:"Mike Treseler" <tres@tc.fluke.com> wrote in message
:news:3F8F8718.5020103@tc.fluke.com...
:>
:>
:> Neil Zanella wrote:
:>
:> > I would like to ask a question concerning the intended use of component
:> > statements within architecture statements in VHDL. Since when
:> > instantiating different components the component part is optional, why
:> > would anyone want to include it. Even if two entities were defined with
:an
:> > interface with clashing signal names, the scope of those names would not
:> > interfere when those entities are used for instantiation. So why would
:> > anyone want to use an explicit component statement inside an
:architecture?
:>
:> A component is a socket into which you can plug
:> any entity/architecture that fits using a configuration.
:>
:> If there will only be one such module to plug in,
:> as is often the case, then direct instances
:> without component declarations make sense.
:>
:> However, if you expect to plug in a different module in
:> the future, an indirect instance now may simplify
:> the future change while providing backward compatibility
:> with the first design.
:>
:> -- Mike Treseler
:>
:
 
Barry Brown wrote:
So what is the correct syntax for instantiating an entity that is not in
your "work" library? I've never been able to figure out direct
instantiation of Xilinx unisim primitives - either ModelSim or Synplify (or
both) choke on everything I've tried. It seems like this should work...
Click to expand...
I use this, which works in both Synplify and Modelsim:

--synopsys translate_off;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
--synopsys translate_on;
library synplify;
use synplify.attributes.all;

ARCHITECTURE synth OF tmux IS
component ROC
port (
O : out std_logic
);
end component;
-- Synplify attributes
attribute syn_black_box of ROC : component is true;
BEGIN
TRST : ROC
port map(O => reset);


--
My real email is akamail.com@dclark (or something like that).
 
Duane Clark <junkmail@junkmail.com> wrote in message:

ARCHITECTURE synth OF tmux IS
component ROC
port (
O : out std_logic
);
Click to expand...
.... so why is it that VHDL requires the port section to be copied from the
entity declaration to the component declaration? Can't VHDL figure the
information out based on component name matching looking for an entity
that has the same name and using the names from the port section
specified therein?

Thanks,

Neil

end component;
-- Synplify attributes
attribute syn_black_box of ROC : component is true;
BEGIN
TRST : ROC
port map(O => reset);
Click to expand...
 
Neil Zanella wrote:
... so why is it that VHDL requires the port section to be copied from the
entity declaration to the component declaration? Can't VHDL figure the
information out based on component name matching looking for an entity
that has the same name and using the names from the port section
specified therein?
Click to expand...
I am in the habit of putting explicit component declarations into code
to be synthesized, but not into testbench code. Don't really know how I
got into that habit, and really haven't had a reason to change.

--
My real email is akamail.com@dclark (or something like that).
 
Neil Zanella wrote:

... so why is it that VHDL requires the port section to be copied from the
entity declaration to the component declaration? Can't VHDL figure the
information out based on component name matching looking for an entity
that has the same name and using the names from the port section
specified therein?
Click to expand...
A component is an *optional* interface specification
that allows the compiler to complain if a referenced
entity does not match the template. The information
is necessarily redundant, but it is easy work for
many vhdl editors. For emacs menus it's

click, VHDL, PORT, COPY
click, VHDL, PORT, PASTE AS COMP

-- Mike Treseler
 
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