A
ajahn
Guest
Hi,
I just want to know if I missed something...
If you have a toplevel entity with say a bus of single std_logic
signals of inout mode and want to use this within a component, you
can't really combine the signals to a std_logic_vector... right? That
means you have to use the single inout signals on the component as well
and use the toplevel entity signal names as actuals for the component
instantiation.
Two reasons:
- if you use a signal assignment to map the signals into a vector, its
only one direction...
- u can't use array aggregates as actuals, beause they're not locally
static, so a concatenation of type data => d4 & d3 & d2 & d1 would
not work...
Do you guys agree or did I miss a possibility?
Cheers
Andreas
I just want to know if I missed something...
If you have a toplevel entity with say a bus of single std_logic
signals of inout mode and want to use this within a component, you
can't really combine the signals to a std_logic_vector... right? That
means you have to use the single inout signals on the component as well
and use the toplevel entity signal names as actuals for the component
instantiation.
Two reasons:
- if you use a signal assignment to map the signals into a vector, its
only one direction...
- u can't use array aggregates as actuals, beause they're not locally
static, so a concatenation of type data => d4 & d3 & d2 & d1 would
not work...
Do you guys agree or did I miss a possibility?
Cheers
Andreas