M
Michael Eichler
Guest
Hello,
In the small example below both Modelsim and NCSim do complain about the
type of p3 in the line
b_out(bus_names'pos(p3)) <= p3;
Modelsim Error Message:
** Error: ../test_name_conflict.vhd(34): Signal "p3" is type std_ulogic;
expecting type bus_names.
But the required argument type is known to the compiler (bus_names) and
is visible. So the correct object could be selected by the compiler (p3
of enum bus_names instead of the port p3). Are the compilers wrong or
did I miss something important?
-- ******************************************************************
PACKAGE name_conflict_pkg IS
TYPE bus_names IS (b1, b2, p3);
END name_conflict_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY work;
USE work.name_conflict_pkg.ALL;
ENTITY test_name_conflict IS
PORT (p1 : IN std_ulogic;
p2 : IN std_ulogic;
p3 : IN std_ulogic;
b_out : OUT std_ulogic_vector(bus_names'pos(bus_names'high)
DOWNTO
bus_names'pos(bus_names'low)));
END test_name_conflict;
ARCHITECTURE test OF test_name_conflict IS
BEGIN -- test
b_out(bus_names'pos(b1)) <= p1;
b_out(bus_names'pos(b2)) <= p2;
-- Why is this an name conflict with Port p3?
-- Type of required argument is known to the compiler
-- See LRM 1076-1993 Section 10; Rule 255 ??
b_out(bus_names'pos(p3)) <= p3;
-- This will work:
-- b_out(bus_names'pos(bus_names'high)) <= p3;
END test;
-- ******************************************************************
In the small example below both Modelsim and NCSim do complain about the
type of p3 in the line
b_out(bus_names'pos(p3)) <= p3;
Modelsim Error Message:
** Error: ../test_name_conflict.vhd(34): Signal "p3" is type std_ulogic;
expecting type bus_names.
But the required argument type is known to the compiler (bus_names) and
is visible. So the correct object could be selected by the compiler (p3
of enum bus_names instead of the port p3). Are the compilers wrong or
did I miss something important?
-- ******************************************************************
PACKAGE name_conflict_pkg IS
TYPE bus_names IS (b1, b2, p3);
END name_conflict_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY work;
USE work.name_conflict_pkg.ALL;
ENTITY test_name_conflict IS
PORT (p1 : IN std_ulogic;
p2 : IN std_ulogic;
p3 : IN std_ulogic;
b_out : OUT std_ulogic_vector(bus_names'pos(bus_names'high)
DOWNTO
bus_names'pos(bus_names'low)));
END test_name_conflict;
ARCHITECTURE test OF test_name_conflict IS
BEGIN -- test
b_out(bus_names'pos(b1)) <= p1;
b_out(bus_names'pos(b2)) <= p2;
-- Why is this an name conflict with Port p3?
-- Type of required argument is known to the compiler
-- See LRM 1076-1993 Section 10; Rule 255 ??
b_out(bus_names'pos(p3)) <= p3;
-- This will work:
-- b_out(bus_names'pos(bus_names'high)) <= p3;
END test;
-- ******************************************************************