Compile verilog module-instances

[Raf Karakiewicz]

Hi,

I am running a spectreSverilog simulations and as long as my top-level
verilog module contains no other module instances everything works fine.
If now I add a module instance I get the following error during
netlisting:

Error! Module or primitive (inShiftReg) not defined


I have an inShiftReg cellview with a functional view containing the
verilog code. How do I make cadence compile all the modules together?

Can anyone help me?


Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu