Compile time

[gervaz]

Hi, sorry if I may be ot, but I just need a simple answer: in many
benchmark I found the result of the compile time used for a particular
core. Now, compile time what does it means? Syntesys, optimization and
mapping or syntesys, optimization, mapping and p&r?

Thanks, Mattia

 

[Alex]

On Thu, 19 Feb 2009 15:20:21 -0800, gervaz wrote:

Hi, sorry if I may be ot, but I just need a simple answer: in many
benchmark I found the result of the compile time used for a particular
core. Now, compile time what does it means? Syntesys, optimization and
mapping or syntesys, optimization, mapping and p&r?

Thanks, Mattia

Different tools could refer to "compilation time" with different
meanings. For something like Quartus it could mean the whole synthesis
and place and route process, for a simulator it would just be the
compilation of the VHDL code into whatever binary format the simulator's
library takes. You have to look at what the benchmark is comparing to
really decide.

 

[mattia]

Il Sun, 22 Feb 2009 08:14:36 -0600, Alex ha scritto:

On Thu, 19 Feb 2009 15:20:21 -0800, gervaz wrote:

Hi, sorry if I may be ot, but I just need a simple answer: in many
benchmark I found the result of the compile time used for a particular
core. Now, compile time what does it means? Syntesys, optimization and
mapping or syntesys, optimization, mapping and p&r?

Thanks, Mattia

Different tools could refer to "compilation time" with different
meanings. For something like Quartus it could mean the whole synthesis
and place and route process, for a simulator it would just be the
compilation of the VHDL code into whatever binary format the simulator's
library takes. You have to look at what the benchmark is comparing to
really decide.

I was trying to figure out what Altera inteded for "compile time" here:
http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/
architecture/performance/st3-
opencores.html#Benchmarking_and_Stamping_Methodology but with no success.
Any hint?