Compile OK but simulation fails

[Marios Barlas]

Hello every1,

I am new to VHDL just working on my first code. I am trying to realize an sqrt(x) function in a sequential wax and simulate it with Modelsim.

My code looks like this :

use ieee.numeric_std.ALL;

entity sqroot is
generic (constant NBITS : natural := 8); --design implementation
port (
signal arg : in std_logic_vector(NBITS-1 downto 0);
signal roundup : in std_logic := '0'; --determine if roundup is done or not
signal sqroot : out std_logic_vector(NBITS/2 downto 0));
end entity sqroot;

architecture rtl of sqroot is
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

--Internal signal definitions
signal delta : unsigned(NBITS-1 downto 0) := (0 => '1', others => '0');

begin

process( arg, roundup )

--Internal variable definitions
variable delta_int : integer := 1;
variable sqroot_int : integer :=0;
variable res_int : integer := to_integer(unsigned(arg));

begin

delta <= delta sll (NBITS-2); -- shifted // temp = delta^(NBITS-2)
delta_int := to_integer(delta);

while (delta_int >= 1) loop
if ( (sqroot_int + delta_int) <= res_int ) then
res_int := res_int -(sqroot_int + delta_int);
sqroot_int := sqroot_int + 2*delta_int;
end if;

sqroot_int := sqroot_int/2;
delta_int := delta_int/4;
end loop;

if ( (roundup = '1') and (res_int > sqroot_int) ) then
sqroot_int := sqroot_int + 1;
end if;

sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length));

end process;

end architecture rtl;

I end up with an error on the sqroot line right before the end :

sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length));

fatal error simulation terminated.

I don't really understand what that error is associated to.
Any1 has a hint ?

Thanks in advance
Mario

 

[Brian Drummond]

On Fri, 14 Nov 2014 07:29:22 -0800, Marios Barlas wrote:

Hello every1,

I am new to VHDL just working on my first code. I am trying to realize
an sqrt(x) function in a sequential wax and simulate it with Modelsim.

My code looks like this :

use ieee.numeric_std.ALL;

entity sqroot is
generic (constant NBITS : natural := 8); --design implementation port
(
signal sqroot : out std_logic_vector(NBITS/2 downto 0));
end entity sqroot;


I end up with an error on the sqroot line right before the end :

sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length));

You have probably already solved this, but for completeness : there is
both an entity and signal with the same name sqroot, so some expressions
like sqroot'length may be ambiguous...

- Brian

 

[Marios Barlas]

Τη Σάββατο, 15 Νοεμβρίου 2014 1:03:52 μ.μ. UTC+1, ο χρήστης Brian Drummond έγραψε:

On Fri, 14 Nov 2014 07:29:22 -0800, Marios Barlas wrote:

Hello every1,

I am new to VHDL just working on my first code. I am trying to realize
an sqrt(x) function in a sequential wax and simulate it with Modelsim.

My code looks like this :

use ieee.numeric_std.ALL;

entity sqroot is
generic (constant NBITS : natural := 8); --design implementation port
(
signal sqroot : out std_logic_vector(NBITS/2 downto 0));
end entity sqroot;


I end up with an error on the sqroot line right before the end :

sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length));

You have probably already solved this, but for completeness : there is
both an entity and signal with the same name sqroot, so some expressions
like sqroot'length may be ambiguous...

- Brian

Thanks for the answer Brian! Yes I resolved it, I'm sorry for the stupid questions of a rookie but newsgroups are in my opinion the best way to ask experienced people.

With appreciation,
Marios Barlas

 

On Saturday, November 15, 2014 4:29:26 AM UTC+13, Marios Barlas wrote:

My code looks like this :

use ieee.numeric_std.ALL;


I end up with an error on the sqroot line right before the end :

sqroot <= std_logic_vector(to_unsigned(sqroot_int,sqroot'length));

The to_unsigned function found in package numeric_std expects a natural. Passing it a negative value would be erroneous.

function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;


The variable I_VAL (and RESULT) are dynamically elaborated. Assigning a negative ARG would fail.

The signature for TO_UNSIGNED allows an integer (a natural is a constrained integer, a subtype of the type integer).

That would speak to a an algorithm implementation issue.

You might consider adding an integer signal to receive sq_root_int, and comment out the above statement so you can see what's going on.

It might help for others to know what your input was for the failed case (arg, roundup).