Compile Error in RAM Module

C

Chris

Guest
The Icarus Verilog compiler keeps reporting an error on a RAM module
declaration.
Here is the module:

// Memory Module
// ==================================================================
module MEM16X32(data,address,wr,rd);
parameter delay = 10;
inout [31:0] data;
input [ 3:0] address;
input wr,rd;

reg [31:0] memoryspace [15:0];
wire [31:0] localdataout;
wire outputenable;
// The value at the current address is
// always at the input of the buffer
assign localdataout = memoryspace[address];
// A rising edge of the write pulse
// actually puts the data into memory
always @(negedge wr)
#delay memoryspace[address] <= data;
// Write must be low to prevent
// conflicts during a read!
and #delay u1(outputenable,rd,~wr);
// If a read occurs then just
// enable the output wires onto the bus.
tribuf 32 #delay outbuf(data, localdataout, outputenable); // <<<
Parse Error Here
endmodule

module tribuf (q,d,oe); // if OE=1 then Q=D, else Q=Z
output q;
input d,oe;
bufif1 tsb (q,d,oe);
endmodule

It reports invalid Module Instantiation on the line:
tribuf 32 #delay outbuf(data, localdataout, outputenable); // <<<
Parse Error Here

I can't figure out what is wrong here. Looks fine to me. Anyone have an
idea?

Chris.
 
Hi Chris,

The line syntax is wrong, you should not have "32" here. What do you intend
to do with this "32"?

Regards,
Serge

"Chris" <nospam@nospam.com> a écrit dans le message de news:
hNSdnZHgM_Us1IPYnZ2dnUVZ_rSdnZ2d@comcast.com...
The Icarus Verilog compiler keeps reporting an error on a RAM module
declaration.
Here is the module:

// Memory Module
// ==================================================================
module MEM16X32(data,address,wr,rd);
parameter delay = 10;
inout [31:0] data;
input [ 3:0] address;
input wr,rd;

reg [31:0] memoryspace [15:0];
wire [31:0] localdataout;
wire outputenable;
// The value at the current address is
// always at the input of the buffer
assign localdataout = memoryspace[address];
// A rising edge of the write pulse
// actually puts the data into memory
always @(negedge wr)
#delay memoryspace[address] <= data;
// Write must be low to prevent
// conflicts during a read!
and #delay u1(outputenable,rd,~wr);
// If a read occurs then just
// enable the output wires onto the bus.
tribuf 32 #delay outbuf(data, localdataout, outputenable); //
Parse Error Here
endmodule

module tribuf (q,d,oe); // if OE=1 then Q=D, else Q=Z
output q;
input d,oe;
bufif1 tsb (q,d,oe);
endmodule

It reports invalid Module Instantiation on the line:
tribuf 32 #delay outbuf(data, localdataout, outputenable); //
Parse Error Here

I can't figure out what is wrong here. Looks fine to me. Anyone have an
idea?

Chris.
Click to expand...
 
Thanks. I thought that Verilog could apply a single param module across a
array of wires by calling it a number of times, but I guess not. I changed
it to what is below. This works but, is there a way I can call the bufif1
func 32 times in a "for" loop block to cover the 32 wires?

Chris.

tribuf32 outbuf(data, localdataout, outputenable);

module tribuf32 (q,d,oe); // if OE=1 then Q=D, else Q=Z
output [31:0] q;
input [31:0] d;
input oe;
bufif1 tsb00 (q[00],d[00],oe);
bufif1 tsb01 (q[01],d[01],oe);
bufif1 tsb02 (q[02],d[02],oe);
bufif1 tsb03 (q[03],d[03],oe);
bufif1 tsb04 (q[04],d[04],oe);
bufif1 tsb05 (q[05],d[05],oe);
bufif1 tsb06 (q[06],d[06],oe);
bufif1 tsb07 (q[07],d[07],oe);
bufif1 tsb08 (q[08],d[08],oe);
bufif1 tsb09 (q[09],d[09],oe);
bufif1 tsb10 (q[10],d[10],oe);
bufif1 tsb11 (q[11],d[11],oe);
bufif1 tsb12 (q[12],d[12],oe);
bufif1 tsb13 (q[13],d[13],oe);
bufif1 tsb14 (q[14],d[14],oe);
bufif1 tsb15 (q[15],d[15],oe);
bufif1 tsb16 (q[16],d[16],oe);
bufif1 tsb17 (q[17],d[17],oe);
bufif1 tsb18 (q[18],d[18],oe);
bufif1 tsb19 (q[19],d[19],oe);
bufif1 tsb20 (q[20],d[20],oe);
bufif1 tsb21 (q[21],d[21],oe);
bufif1 tsb22 (q[22],d[22],oe);
bufif1 tsb23 (q[23],d[23],oe);
bufif1 tsb24 (q[24],d[24],oe);
bufif1 tsb25 (q[25],d[25],oe);
bufif1 tsb26 (q[26],d[26],oe);
bufif1 tsb27 (q[27],d[27],oe);
bufif1 tsb28 (q[28],d[28],oe);
bufif1 tsb29 (q[29],d[29],oe);
bufif1 tsb30 (q[30],d[30],oe);
bufif1 tsb31 (q[31],d[31],oe);
endmodule // tribuf32
 
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Chris wrote:
Thanks. I thought that Verilog could apply a single param module across a
array of wires by calling it a number of times, but I guess not. I changed
it to what is below. This works but, is there a way I can call the bufif1
func 32 times in a "for" loop block to cover the 32 wires?
Click to expand...
You are using terms and lingo in a way that nobody here understands.
I *think* you want something like this:

bufif tsb [31:0] (data,localdataout,outputenable);

or this:

assign data = outputenable? localdataout : 32'bz;



- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Thanks, that does the trick. Sorry for my bad description. It's been 10
years since I wrote verilog so I am woefully rusty at it. I am using your
iVerilog. It has been a big help.

Thanks again, Chris.




"Stephen Williams" <spamtrap@icarus.com> wrote in message
news:rMOdnahKG9gIRoLYnZ2dnUVZ_vOdnZ2d@giganews.com...
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Chris wrote:
Thanks. I thought that Verilog could apply a single param module across
a
array of wires by calling it a number of times, but I guess not. I
changed
it to what is below. This works but, is there a way I can call the
bufif1
func 32 times in a "for" loop block to cover the 32 wires?

You are using terms and lingo in a way that nobody here understands.
I *think* you want something like this:

bufif tsb [31:0] (data,localdataout,outputenable);

or this:

assign data = outputenable? localdataout : 32'bz;



- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Version: GnuPG v1.4.2 (GNU/Linux)
Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org

iD8DBQFFH9uTrPt1Sc2b3ikRAnnaAJ9mbKOhD+/VMmrX4lk8A+pFByzsfwCgwyk8
N0MwQZfPpbPRhu2PO4k9UzQ=
=v5Vv
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Click to expand...
 
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