Compile 30% of my multipliers with LUT?

K

Kelvin

Guest
Hi, there:

I am compiling a partial design with XST. I can only use 24 multipliers in
my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't want to
modify the RTL codes...
How may I handle this situation?

"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK makes all
multipliers with
block multiplers...sigh...

Thanks for your suggesiton...

Kelvin
 
"Kelvin" <student@nowhere.com> wrote in message
news:40e4f466@news.starhub.net.sg...
Hi, there:
I am compiling a partial design with XST. I can only use 24 multipliers in
my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't want
to
modify the RTL codes...
How may I handle this situation?
"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK makes
all
multipliers with
block multiplers...sigh...
Thanks for your suggesiton...
Kelvin
Click to expand...

If you leave the sythesis tool to its own devices does it not use as many
dedicated multipliers as it can then implement the rest combinatorially?

That's what I would have expected to happen.



Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone Based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk
 
Kelvin wrote:
I am compiling a partial design with XST. I can only use 24
multipliers in my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't
want to modify the RTL codes...
How may I handle this situation?

"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
makes all multipliers with
block multiplers...sigh...
Click to expand...
Tell the synth that you are compiling for a smaller chip?
 
Tim wrote:

Kelvin wrote:

I am compiling a partial design with XST. I can only use 24
multipliers in my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't
want to modify the RTL codes...
How may I handle this situation?

"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
makes all multipliers with
block multiplers...sigh...


Tell the synth that you are compiling for a smaller chip?
Click to expand...


Looks to me that MULT_STYLE is an attribute as well as a synthesis
option meaning you can either use it globally as it sounds you may have
done or attach it on certain modules or certain signals to specify how
to implement individual multipliers in your code. As a quick test, I
wrote the following code and got one multiplier built from LUTs and the
other using the MULT18X18S block:

`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is lut;
reg [21:0] Z; // synthesis attribute mult_style of Z is block;

always @(posedge CLK)
Z <= X * Y;

always @(posedge CLK)
C <= A * B;

endmodule


-- Brian
 
Thank you Brian! It seems to work with me.

Best Regards,
Kelvin







"Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message
news:cc4jjh$4pg1@xco-news.xilinx.com...
Tim wrote:

Kelvin wrote:

I am compiling a partial design with XST. I can only use 24
multipliers in my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't
want to modify the RTL codes...
How may I handle this situation?

"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
makes all multipliers with
block multiplers...sigh...


Tell the synth that you are compiling for a smaller chip?





Looks to me that MULT_STYLE is an attribute as well as a synthesis
option meaning you can either use it globally as it sounds you may have
done or attach it on certain modules or certain signals to specify how
to implement individual multipliers in your code. As a quick test, I
wrote the following code and got one multiplier built from LUTs and the
other using the MULT18X18S block:

`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is lut;
reg [21:0] Z; // synthesis attribute mult_style of Z is block;

always @(posedge CLK)
Z <= X * Y;

always @(posedge CLK)
C <= A * B;

endmodule


-- Brian
Click to expand...
 
However, the following code seemed fail...Maybe D & E are removed in the
synthesis.





`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is block;
reg [21:0] Z;
wire [21:0] D;
wire [21:0] E;

assign D = X * Y; // synthesis attribute mult_style of D is lut;
assign E = A * B; // synthesis attribute mult_style of E is block;

always @(posedge CLK)
Z <= D + E;

always @(posedge CLK)
C <= A * B - X * Y;

endmodule


"Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message
news:cc4jjh$4pg1@xco-news.xilinx.com...
Tim wrote:

Kelvin wrote:

I am compiling a partial design with XST. I can only use 24
multipliers in my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't
want to modify the RTL codes...
How may I handle this situation?

"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
makes all multipliers with
block multiplers...sigh...


Tell the synth that you are compiling for a smaller chip?





Looks to me that MULT_STYLE is an attribute as well as a synthesis
option meaning you can either use it globally as it sounds you may have
done or attach it on certain modules or certain signals to specify how
to implement individual multipliers in your code. As a quick test, I
wrote the following code and got one multiplier built from LUTs and the
other using the MULT18X18S block:

`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is lut;
reg [21:0] Z; // synthesis attribute mult_style of Z is block;

always @(posedge CLK)
Z <= X * Y;

always @(posedge CLK)
C <= A * B;

endmodule


-- Brian
Click to expand...
 
never mind, it does apply to a wire also...Can test with these code...

assign D = A * Y; // synthesis attribute mult_style of D is lut;
assign E = X * B; // synthesis attribute mult_style of E is block;


"Kelvin" <student@nowhere.com> wrote in message
news:40e8f2bb@news.starhub.net.sg...
However, the following code seemed fail...Maybe D & E are removed in the
synthesis.





`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is block;
reg [21:0] Z;
wire [21:0] D;
wire [21:0] E;

assign D = X * Y; // synthesis attribute mult_style of D is lut;
assign E = A * B; // synthesis attribute mult_style of E is block;

always @(posedge CLK)
Z <= D + E;

always @(posedge CLK)
C <= A * B - X * Y;

endmodule


"Brian Philofsky" <brian.philofsky@no_xilinx_spam.com> wrote in message
news:cc4jjh$4pg1@xco-news.xilinx.com...


Tim wrote:

Kelvin wrote:

I am compiling a partial design with XST. I can only use 24
multipliers in my portion of a V2-6000 chip...
However, the RTL has 35 multipliers...
Now I need to compile the other 11 multipliers with LUT, but I don't
want to modify the RTL codes...
How may I handle this situation?

"-mult_style LUT" makes all multipliers with LUT...AUTO and BLOCK
makes all multipliers with
block multiplers...sigh...


Tell the synth that you are compiling for a smaller chip?





Looks to me that MULT_STYLE is an attribute as well as a synthesis
option meaning you can either use it globally as it sounds you may have
done or attach it on certain modules or certain signals to specify how
to implement individual multipliers in your code. As a quick test, I
wrote the following code and got one multiplier built from LUTs and the
other using the MULT18X18S block:

`timescale 1ns/1ps

module mult_style_test (A, B, C, CLK, X, Y, Z);

input [10:0] A;
input [10:0] B;
output [21:0] C;
input CLK;
input [10:0] X;
input [10:0] Y;
output [21:0] Z;

reg [21:0] C; // synthesis attribute mult_style of C is lut;
reg [21:0] Z; // synthesis attribute mult_style of Z is block;

always @(posedge CLK)
Z <= X * Y;

always @(posedge CLK)
C <= A * B;

endmodule


-- Brian
Click to expand...
 
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