Compilation order of verilog files in NCVerilog/VCS simulato

[Kesav]

Hi..

Recently, I started learning to do timing simulation using NCVerilog
and VCS simulator. I have the following problem of specifying the
correct delay mode compiler directive..

In the testbench, I specified `delay_mode_distributed and
in the DUT (design under test) I specified `delay_mode_path (The sdf
file is called using $sdf_annotate in DUT)...

With this set up , my understanding is that, the testbench should
execute under distributed delay;
and the DUT should execute under path delay;

If that is true, then I have the following strange observation:

During compilation of verilog file, If I first compile testbench; and
then compile DUT....Then there is no problem..The testbench is executed
with distributed delay; and DUT with path delay...

But, if we compile, DUT first; and then Testbench...In this case, the
DUT is also executed under distributed mode instead of path mode...This
is kind of wierd...

If anyone of you know the solution for this..please do let me know..It
will be of great help...

Please, let me know if I need to provide any other information..

Thanks,
Kesav..