Guest
Hi All,
I need to simulate a Xilinx based design with GHDL. Therefore I needed
to compile the
XilinxCoreLib.
I've prepared a python script to make it automatically (xcl is a
symlink to XilinxCoreLib
sources)
#!/usr/bin/python
import os
plik=open("xcl/vhdl_analyze_order","r")
command="ghdl -a --work=xilinxcorelib "
while True:
line=plik.readline()
if line=="":
break
line=line.strip()
if line != "":
if line[0]!="#":
command=command+" xcl/"+line
print(command)
os.system(command)
Everything works perfectly, but finally I get the error message:
xcl/c_addsub_v8_0.vhd:807:36:warning: universal integer bound must be
numeric literal or attribute
xcl/c_addsub_v8_0.vhd:811:37:warning: universal integer bound must be
numeric literal or attribute
xcl/c_compare_v8_0.vhd:344:5: condition must be a static expression
xcl/c_compare_v8_0.vhd:350:5: condition must be a static expression
xcl/c_compare_v8_0.vhd:351:7: condition must be a static expression
xcl/c_compare_v8_0.vhd:352:9: condition must be a static expression
xcl/c_compare_v8_0.vhd:355:9: condition must be a static expression
xcl/c_compare_v8_0.vhd:359:7: condition must be a static expression
xcl/c_compare_v8_0.vhd:360:9: condition must be a static expression
xcl/c_compare_v8_0.vhd:363:9: condition must be a static expression
/usr/lib/ghdl/bin/ghdl: compilation error
Does anybody know how to workaround this problem? Is it a GHDL problem
or
XilinxCoreLib does not conform to the standard?
--
TIA & Regards,
Wojtek Zabolotny
I need to simulate a Xilinx based design with GHDL. Therefore I needed
to compile the
XilinxCoreLib.
I've prepared a python script to make it automatically (xcl is a
symlink to XilinxCoreLib
sources)
#!/usr/bin/python
import os
plik=open("xcl/vhdl_analyze_order","r")
command="ghdl -a --work=xilinxcorelib "
while True:
line=plik.readline()
if line=="":
break
line=line.strip()
if line != "":
if line[0]!="#":
command=command+" xcl/"+line
print(command)
os.system(command)
Everything works perfectly, but finally I get the error message:
xcl/c_addsub_v8_0.vhd:807:36:warning: universal integer bound must be
numeric literal or attribute
xcl/c_addsub_v8_0.vhd:811:37:warning: universal integer bound must be
numeric literal or attribute
xcl/c_compare_v8_0.vhd:344:5: condition must be a static expression
xcl/c_compare_v8_0.vhd:350:5: condition must be a static expression
xcl/c_compare_v8_0.vhd:351:7: condition must be a static expression
xcl/c_compare_v8_0.vhd:352:9: condition must be a static expression
xcl/c_compare_v8_0.vhd:355:9: condition must be a static expression
xcl/c_compare_v8_0.vhd:359:7: condition must be a static expression
xcl/c_compare_v8_0.vhd:360:9: condition must be a static expression
xcl/c_compare_v8_0.vhd:363:9: condition must be a static expression
/usr/lib/ghdl/bin/ghdl: compilation error
Does anybody know how to workaround this problem? Is it a GHDL problem
or
XilinxCoreLib does not conform to the standard?
--
TIA & Regards,
Wojtek Zabolotny