S
srinukasam
Guest
Hello
In my design what i need is to compare 2 bit vectors( one is of multiple
lenth with the other one) parallel with generate statement. I wrote design
and test benches. But at the time of compilation its giving errors with
generate command. Could you please see once and mail me what is the error
with my design.
DESIGN:------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use work.contr_pak.all;
ENTITY nest_addr IS
generic(pstate_width:integer :=8;
mem_width:integer:=128; --out from mem..in to logic
no_of_ns: integer:=16; --for array size .this block
index: integer :=4);
port( clk :in std_logic;
diff_states: in std_logic_vector(mem_width-1 downto 0 );
pstate: in std_logic_vector(pstate_width-1 downto 0);
data ut std_logic_vector(index-1 downto 0));
END ENTITY nest_addr;
--
ARCHITECTURE nest_addr_beh OF nest_addr IS
type temp is array ( o to no_of_ns-1) of std_logic_vector(0 to
pstate_width-1);
signal temp_c:temp;
signal temp_vect :std_logic_vector (no_of_ns-1 downto 0);
signal data_temp:integer:=0;
begin
assignrocess(diff_states)
variable first:integer:=0;
variable second:integer:=0;
begin
for i in 0 to no_of_ns loop
if i =0 then
temp_c(i)<=diff_states(pstate_width-1 downto 0);
else
first:=first+pstate_width;
second:=first+(pstate_width-1);
temp_c(i)<= diff_states(second downto first);
end if;
end loop;
end process assign;
ns:for i in 0 to no_of_ns-1 generate
if (temp_c(i)= pstate) then -- THIS STATEMENT SHOWS THE
ERROR:
data_temp<=i;
--else
end if;
end generate ns;
conv: process(data_temp)
begin
data<=int_to_vect(4,data_temp);
end process;
END ARCHITECTURE nest_addr_beh;
THANK YOU
In my design what i need is to compare 2 bit vectors( one is of multiple
lenth with the other one) parallel with generate statement. I wrote design
and test benches. But at the time of compilation its giving errors with
generate command. Could you please see once and mail me what is the error
with my design.
DESIGN:------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use work.contr_pak.all;
ENTITY nest_addr IS
generic(pstate_width:integer :=8;
mem_width:integer:=128; --out from mem..in to logic
no_of_ns: integer:=16; --for array size .this block
index: integer :=4);
port( clk :in std_logic;
diff_states: in std_logic_vector(mem_width-1 downto 0 );
pstate: in std_logic_vector(pstate_width-1 downto 0);
data ut std_logic_vector(index-1 downto 0));
END ENTITY nest_addr;
--
ARCHITECTURE nest_addr_beh OF nest_addr IS
type temp is array ( o to no_of_ns-1) of std_logic_vector(0 to
pstate_width-1);
signal temp_c:temp;
signal temp_vect :std_logic_vector (no_of_ns-1 downto 0);
signal data_temp:integer:=0;
begin
assignrocess(diff_states)
variable first:integer:=0;
variable second:integer:=0;
begin
for i in 0 to no_of_ns loop
if i =0 then
temp_c(i)<=diff_states(pstate_width-1 downto 0);
else
first:=first+pstate_width;
second:=first+(pstate_width-1);
temp_c(i)<= diff_states(second downto first);
end if;
end loop;
end process assign;
ns:for i in 0 to no_of_ns-1 generate
if (temp_c(i)= pstate) then -- THIS STATEMENT SHOWS THE
ERROR:
data_temp<=i;
--else
end if;
end generate ns;
conv: process(data_temp)
begin
data<=int_to_vect(4,data_temp);
end process;
END ARCHITECTURE nest_addr_beh;
THANK YOU