compilation directive

Guest
hello

is it possible in VHDL to add compilation directive like this ?

ifdef simulation timer=100
ifdef synthesis timer=100000

I don't find information on this

thanks
 
<fpga.vhdl.designer@gmail.com> wrote in message
news:1178792309.817397.278960@o5g2000hsb.googlegroups.com...
hello

is it possible in VHDL to add compilation directive like this ?

ifdef simulation timer=100
ifdef synthesis timer=100000

I don't find information on this

thanks
No, but is is possible to create a function that returns what you want.
Click to expand...
Instead of 'simulation' and 'synthesis' in your example you could instead
have a constant called 'What_Im_Doing' and a function. Below is a sketch of
what I had in mind as a possible way to go about it.

function Get_Timer(What_Im_Doing: string) return natural is
begin
if (What_Im_Doing = "simulation") then
return(100);
elsif (What_Im_Doing = "synthesis") then
return(100000);
else
assert FALSE
report "OOPS! Invalid value for 'What_Im_Doing' (" & What_Im_Doing
& ")"
severity ERROR;
end if;
end function Get_Timer;
constant What_Im_Doing: string := "simulation"; -- As an example...could
also be brought in as a generic to your entity
constant Timer: natural := Get_Timer(What_Im_Doing);

KJ
 
On Thu, 10 May 2007 07:16:41 -0400, "KJ" <kkjennings@sbcglobal.net>
wrote:

fpga.vhdl.designer@gmail.com> wrote in message
news:1178792309.817397.278960@o5g2000hsb.googlegroups.com...
hello

is it possible in VHDL to add compilation directive like this ?

ifdef simulation timer=100
ifdef synthesis timer=100000

No, but is is possible to create a function that returns what you want.

function Get_Timer(What_Im_Doing: string) return natural is
begin
if (What_Im_Doing = "simulation") then
return(100);
Click to expand...
Instead of strings, couldn't the function simply incorporate a synthesis
pragma?

function setTimer return natural is
begin
-- synthesis translate off
return 10000;
-- synthesis translate on
return 100;
end function setTimer;

(untested : and the pragma may be different for your synthesis tool)

- Brian
 
Hi,
I have done this with generics.

For synthesis, a default value on the entity sets the generic
value and for simulation, the generic is mapped in the
instantiation of the DUT in the testbench.

No pragma's required. Also if you ever want to run the
simulation at a slow rate (perhaps one time through), you
can use a configuration to change the value.

Cheers,
Jim

entity TimerBlk is
generic (
TIMER_INIT_VAL : integer := 100000 -- synthesis value
) ;
port (
. . .
);
end TimerBlk ;


entity TbTimerBlk is
end TbTimerBlk ;

architecture Test1 of TbTimerBlk is
.. . .
begin
U_TimerBlk : TimerBlk
generic map (TIMER_INIT_VAL => 100) -- value for simulatoin
port map (
. . .
) ;

. . .
end Test1 ;


hello

is it possible in VHDL to add compilation directive like this ?

ifdef simulation timer=100
ifdef synthesis timer=100000

I don't find information on this

thanks
Click to expand...
 
KJ wrote:

function Get_Timer(What_Im_Doing: string) return natural is
begin
if (What_Im_Doing = "simulation") then
return(100);
elsif (What_Im_Doing = "synthesis") then
return(100000);
else
assert FALSE
report "OOPS! Invalid value for 'What_Im_Doing' (" &
What_Im_Doing
& ")"
severity ERROR;
end if;
end function Get_Timer;
Click to expand...
Why abuse type string for this? This calls for an enumeration type! By doing
that, no wrong value can be passed to the function, hence no error checking
needed:

type What_Im_Doing_type is (simulation, synthesis);
function Get_Timer(What_Im_Doing: What_Im_Doing_type) return natural is
begin
case What_Im_Doing is
when simulation =>
return 100;
when synthesis =>
return 100000;
end case;
end function Get_Timer;

Hmm, and why not just a table?

type What_Im_Doing_type is (simulation, synthesis);
type Get_Timer_type is array(What_Im_Doing_type) of natural;
constant Get_Timer: Get_Timer_type :=
(
simulation => 100,
synthesis => 100000
);

But now I got carried a way a bit...

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
"Paul Uiterlinden" <puiterl@notaimvalley.nl> wrote in message
news:46438874$0$324$e4fe514c@news.xs4all.nl...
KJ wrote:

Why abuse type string for this? This calls for an enumeration type! By
doing
that, no wrong value can be passed to the function, hence no error
checking
needed:
snip
Hmm, and why not just a table?

snip
Click to expand...

Many ways to skin a cat. I thought best to just keep it simple to
understand based on my perception of the original poster's skill.level.

KJ
 
<snip
Instead of strings, couldn't the function simply incorporate a synthesis
pragma?

snip
(untested : and the pragma may be different for your synthesis tool)
Click to expand...
And that's why I wouldn't use the pragma in this instance...you have the
potential of creating something that compiles one way with one tool and
another with a different tool with no real savings other than a couple of
keystrokes.

KJ
 
YES! With generics you can drive generate statements that work
similarly to conditional compiling. And/or you can derive constants,
either directly, or through expressions or functions of the
generic(s).

I typically have generics on the top level synthesis entity defined
with default values as appropriate for synthesis, and then override
those default values in the entity instantiation in the test bench if
necessary.

And, best of all, most VHDL compilers (synthesis and simulation) have
the ability to set the values for top-level generics via command line
options (what the OP was interested in).

Andy

On May 10, 10:12 am, Jim Lewis <j...@synthworks.com> wrote:
Hi,
I have done this with generics.

For synthesis, a default value on the entity sets the generic
value and for simulation, the generic is mapped in the
instantiation of the DUT in the testbench.

No pragma's required. Also if you ever want to run the
simulation at a slow rate (perhaps one time through), you
can use a configuration to change the value.

Cheers,
Jim

entity TimerBlk is
generic (
TIMER_INIT_VAL : integer := 100000 -- synthesis value
) ;
port (
. . .
);
end TimerBlk ;

entity TbTimerBlk is
end TbTimerBlk ;

architecture Test1 of TbTimerBlk is
. . .
begin
U_TimerBlk : TimerBlk
generic map (TIMER_INIT_VAL => 100) -- value for simulatoin
port map (
. . .
) ;

. . .
end Test1 ;

hello

is it possible in VHDL to add compilation directive like this ?

ifdef simulation timer=100
ifdef synthesis timer=100000

I don't find information on this

thanks
Click to expand...
 
KJ wrote:

Many ways to skin a cat. I thought best to just keep it simple to
understand based on my perception of the original poster's skill.level.
Click to expand...
That's no excuse to promote bad habits. ;-)
All of course in my humble opinion.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
 
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