Comparision between some Verilog Simulators

R

Rajat Mitra

Guest
I have been in the market for a Verilog Simulator. Having worked at some
rather rigorous chip design outfits for the last 7 or so years, I was
exposed only to the industry standard VCS and NC Verilog tools on Linux and
HPUX..... I know of know other way to do IC design besides doing it with
these tools on Unix Platforms..but am open to learning how to use these
tools on Win+PC. Now on inquiring on what these tools cost, I found the
amounts to be commensurate with that of putting a down payment on a house.
So here I am looking for advice; I recently learned that Cadence and Mentor
have NC-Verilog and ModelSim Verilog available on Win PC platforms and at a
price that is somewhat affordable ( <$5K). I also found another Verilog
Compiler called Silos ( Simucad - now Silvaco )..here are my questions -

-Is ModelSim PE a compiled simulator ?? How does it compare in performance
with LE ( Unix Version ) ??
-How does NC Verilog on PC compare in feature / performance with its Unix
counterpart ??
-How does the latest version of NC-Verilog ( PC ) compare with latest
Modelsim PE ??
-Is there a Unix like paradigm for simulating a design on Win+PC ?? In Unix
I typically run simulation in Batch Mode ( using a Makefile ) and then post
process a VCD file generated by the simulator. What is the equivalent of
this on Win+PC ??
-Finally the most reasonably priced Unix Verilog simulator I found was one
offered by Silvaco ( Silos ). Does anyone have experience with this tool ??
Hoe does it compare with the big 3 ( Mentor, Cadence, Synopsys ) ?? Is
compiled or interpreted ?? etc..

I appreciate all the help,

Regards,

Rajat Mitra....
 
Rajat Mitra <rajsaima@yahoo.com> wrote:
....
: -Finally the most reasonably priced Unix Verilog simulator I found was one
: offered by Silvaco ( Silos ). Does anyone have experience with this tool ??
: Hoe does it compare with the big 3 ( Mentor, Cadence, Synopsys ) ?? Is
: compiled or interpreted ?? etc..

CVer from Pragmatic C Software is a commercial offer, Icarus Iverilog a free
offer in the field of Unix Verilog simulators.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<btpqq1$fra$1@news.tu-darmstadt.de>...
Rajat Mitra <rajsaima@yahoo.com> wrote:
...
: -Finally the most reasonably priced Unix Verilog simulator I found was one
: offered by Silvaco ( Silos ). Does anyone have experience with this tool ??
: Hoe does it compare with the big 3 ( Mentor, Cadence, Synopsys ) ?? Is
: compiled or interpreted ?? etc..

CVer from Pragmatic C Software is a commercial offer, Icarus Iverilog a free
offer in the field of Unix Verilog simulators.

Bye
Actually there is also Free Version of CVer available as
well. I believe ther are no limitations. See our web site
for a link ...

rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
...............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools
 
On Sat, 10 Jan 2004 21:08:49 GMT, "Rajat Mitra" <rajsaima@yahoo.com>
wrote:

-Is ModelSim PE a compiled simulator ?? How does it compare in performance
with LE ( Unix Version ) ??
All versions of Modelsim are "compiled". I'm not sure why you care
about its internal workings though.
An evaluation should give you an idea of performance.

From the Modelsim website:
"ModelSim LE is a new product that takes ModelSim PE and puts it on a
Linux platform."

SE is the full version, available on Windows and Unix (not Linux!).
SE has some useful additional features, but it's likely you won't
notice much speed difference unless simulating a gate level design.

The licensing for dual language versions (VHDL+Verilog) is about twice
the cost of a single language version. This may be important if you
are using IP cores written in the other language.

-Is there a Unix like paradigm for simulating a design on Win+PC ?? In Unix
I typically run simulation in Batch Mode ( using a Makefile ) and then post
process a VCD file generated by the simulator. What is the equivalent of
this on Win+PC ??
All the simulators I've used have worked the same on Windows and Unix.
(I haven't used that many though.)

Regards,
Allan.
 
In answer to 2 of your questions:

-How does NC Verilog on PC compare in feature / performance with its Unix
counterpart ??
Cadence has two products for the PC -- NC-Verilog which is same price,
features, and performance of the Unix version and Verilog Desktop which is
the same thing but cheaper with some of the performance options removed.

-Is there a Unix like paradigm for simulating a design on Win+PC ?? In
Unix
I typically run simulation in Batch Mode ( using a Makefile ) and then
post
process a VCD file generated by the simulator. What is the equivalent of
this on Win+PC ??
Both NC-Verilog and Verilog Desktop come with a front-end called nclaunch
which allows you to select the files to use and supply all the options
needed.
 
Modelsim SE does support Linux: http://www.model.com/products/se.asp

Paul

Allan Herriman wrote:
On Sat, 10 Jan 2004 21:08:49 GMT, "Rajat Mitra" <rajsaima@yahoo.com
wrote:

-Is ModelSim PE a compiled simulator ?? How does it compare in performance
with LE ( Unix Version ) ??

All versions of Modelsim are "compiled". I'm not sure why you care
about its internal workings though.
An evaluation should give you an idea of performance.

From the Modelsim website:
"ModelSim LE is a new product that takes ModelSim PE and puts it on a
Linux platform."

SE is the full version, available on Windows and Unix (not Linux!).
SE has some useful additional features, but it's likely you won't
notice much speed difference unless simulating a gate level design.

The licensing for dual language versions (VHDL+Verilog) is about twice
the cost of a single language version. This may be important if you
are using IP cores written in the other language.

-Is there a Unix like paradigm for simulating a design on Win+PC ?? In Unix
I typically run simulation in Batch Mode ( using a Makefile ) and then post
process a VCD file generated by the simulator. What is the equivalent of
this on Win+PC ??

All the simulators I've used have worked the same on Windows and Unix.
(I haven't used that many though.)

Regards,
Allan.
 
On Sun, 11 Jan 2004 21:56:52 -0800, Paul Hartke <phartke@Stanford.EDU>
wrote:

Modelsim SE does support Linux: http://www.model.com/products/se.asp
Ah, good. That must be new in version 5.8.

Regards,
Allan.
 
Allan Herriman wrote:
On Sun, 11 Jan 2004 21:56:52 -0800, Paul Hartke <phartke@Stanford.EDU
wrote:

Modelsim SE does support Linux: http://www.model.com/products/se.asp

Ah, good. That must be new in version 5.8.
It has been supported for a long time. I have used 5.6 and 5.7 SE versions on linux.

--Kim
 

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