comparing the array for generic parameters

[srinukasam]

hello
in my design i need a logic to compare the array (suppose width 16 bit
and
size of 0 to 15) with a vector of 16 bit in parallel and in one clk
cycle.
and need to generate address of array is matching.
AND I NEED THIS FOR GENERIC VARIABLES( FOR ALL 3 PARAMETERS)

thank you
bye

 

[Me]

On Wed, 29 Jun 2005 04:45:47 -0400, srinukasam wrote:

hello
in my design i need a logic to compare the array (suppose width 16 bit
and
size of 0 to 15) with a vector of 16 bit in parallel and in one clk
cycle.
and need to generate address of array is matching.
AND I NEED THIS FOR GENERIC VARIABLES( FOR ALL 3 PARAMETERS)

thank you
bye

Homework?
I hope VHDL teachers in India read this newsgroup.

A.

 

[Ralf Hildebrandt]

srinukasam wrote:

in my design i need a logic to compare the array (suppose width 16 bit
and
size of 0 to 15) with a vector of 16 bit in parallel and in one clk
cycle.
and need to generate address of array is matching.

What part of my last explanation did you not understand?

AND I NEED THIS FOR GENERIC VARIABLES( FOR ALL 3 PARAMETERS)

Which 3 parameters? Your description of the problem is not clear.

Comparing a vector element to a constant or generic parameter is not
different to comparing it to a signal.

Ralf

 

[Andy Peters]

srinukasam wrote:

hello
in my design i need a logic to compare the array (suppose width 16 bit
and
size of 0 to 15) with a vector of 16 bit in parallel and in one clk
cycle.
and need to generate address of array is matching.
AND I NEED THIS FOR GENERIC VARIABLES( FOR ALL 3 PARAMETERS)

Sounds like a job for a content-addressable memory (CAM).
Implementation details are left as an exercise for the reader.

-a